# Jimmy(JS) L.

> Innovative Memory Circuit Design

Location: San Jose, California, United States
Profile: https://flows.cv/jimmyjs

Principal Memory Design Engineer & AI Hardware Lead with 30+ years of expertise in the architecture and circuit design of Flash Memories (3D NAND/NOR), SRAM, Emerging Memories (FeRAM,PCM) and CiM(Compute-in-Memory). Expert in PPA analysis, full-chip verification, and silicon debug across advanced process nodes, including FinFET (16nm to 7nm) and standard CMOS

TECHNICAL SKILLS
•	Design Expertise: Memory Chip Architecture, Core/Periphery Circuitry, Analog Circuits (Charge Pumps, Regulator etc.) Compute-in-Memory (CiM)
•	Verification & Analysis: PPA Optimization, Monte Carlo (HSMC), IR Drop (Totem), EM Simulation, Layout Parameter Extraction (LPE), Failure Analysis.

## Work Experience
### Creator @ Stealth Mode
Jan 2025 – Present | Sunnyvale, California, United States
Design the super low power and high speed circuit.

### Design Team Lead @ ANAFLASH Inc
Jan 2021 – Jan 2024 | San Jose, California, United States
Standard Logic Compatible Embedded Flash Memory IP development 
Battery Powered AI Acceleration Solution by using Analog Compute-in-Memory with Logic-EFLASH

### Technical Director @ Yangtze Memory Technologies
Jan 2016 – Jan 2021 | San Jose, CA
3D NAND Flash Design
- Chip Architecturing/Floor planning and power/signal line planning
- Core area circuit design
- Fullchip simulation/Power network analysis/IR drop and EM simulation

### Senior Staff Engineer @ Qualcomm
Jan 2012 – Jan 2016
Designed various SRAM product(SP, Multi-port, RF, PDP) and OTP memory by using 28nm SOC and 16nm/14nm/10nm/7nm Finfet technology.

### Director Of Design @ Contour Semiconductor
Jan 2007 – Jan 2012 | Billerica, MA
Design of Storage Class Memory (1G NAND compatible spec) product using PCM (phase change memory) technology with NMOS only transistor.

### Director Of Design Engineering @ Winbond Electronics
Jan 2005 – Jan 2007 | San Jose, CA
Designed various density(2M/4M/8M) of Serial Flash Memories. 
Designed Dual IO/ Quad IO Serial Flash Memories
- core area decoding circuit, critical read path design and serial I/O control logic circuit
- various charge pump with reference voltage generator

### Design Manager @ NextFlash Technology
Jan 2000 – Jan 2005 | San Jose, CA
Designed Low voltage HIgh Density(256M) NOR flash memory using virtual ground technology
Designed Serial Flash Memory(4M/16M).

### General Manager @ SK hynix
Jan 1985 – Jan 2000
DRAM, SRAM, Flash memory design


## Contact & Social
- LinkedIn: https://linkedin.com/in/jimmy-js-l-a1895516

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Source: https://flows.cv/jimmyjs
JSON Resume: https://flows.cv/jimmyjs/resume.json
Last updated: 2026-04-13