# Jimmy Lin > Product Leader | Enterprise AI for Supply Chain & SRE Agent Platforms @ NVIDIA Location: San Francisco Bay Area, United States Profile: https://flows.cv/jimmylin ## Work Experience ### Product Lead - Enterprise AI @ NVIDIA Jan 2025 – Present | Santa Clara, California, United States Defined and executed end-to-end AI product initiatives across supply chain and IT, delivering agentic solutions that reimagined workflows, boosted productivity, and drove measurable impact from discovery to deployment. ### Director, Product Management - AI/ML Core Products and Cloud Platform @ SambaNova Systems Jan 2023 – Jan 2025 | Palo Alto, California, United States Led end-to-end product strategy for SambaNova’s multimodal model portfolio, including open-source LLMs, vision-language, embedding, and audio models; defined roadmaps by synthesizing market trends, customer needs, and internal research to accelerate platform adoption and enterprise use case fit. Drove product execution for SambaNova Cloud, a high-performance inference platform offering access to ultra-fast leading generative and reasoning models via open standards-compliant APIs, including Meta's Llamas, DeepSeek-R1, Alibaba's Qwen models, and others. Accelerated adoption and expansion across individual developers and enterprise accounts. ### Sr. Manager, Product Management - AI/ML Products @ SambaNova Systems Jan 2022 – Jan 2023 | Palo Alto, California, United States Owned the strategy and roadmap for SambaNova's LLM product offerings, refining roadmap priorities through market insight and user feedback. Partnered cross-functionally across ML research, GTM, and legal to drive dataset curation, model development, performance optimization, and enterprise sales enablement. Defined use cases with measurable ROI and developed go-to-market materials to support sales, PR, and analyst outreach. ### Sr. Principle Product Manager @ SambaNova Systems Jan 2018 – Jan 2022 | Palo Alto, California, United States Spearheaded competitive analysis and strategy. Built a competitor knowledge base to inform pricing and differentiation. Reduced demo development time by 60% through centralized tooling and a reusable showcase library. Launched a cloud-based developer program that enabled new research publications and deepened ecosystem engagement. ### Sr. Staff, Product Application Lead @ Synopsys Inc Jan 2017 – Jan 2018 | Mountain View, CA Led global multi-disciplinary team of developers and user advocates to define and execute a new product vision. Defined product requirements and led product development from inception to productization. Created new brand awareness by developing a new product strategy which differentiated the new product radically from its past form. Developed rollout strategy with marketing. Created marketing materials used across worldwide user conferences. Onboarded key customers on new product from early access to adaption across a wide range of applications. ### Staff, Product Application Engineer @ Synopsys Inc Jan 2014 – Jan 2017 | Mountain View, CA Product lead for custom place and route and verification. Served as an interface between field sales/support, marketing, and R&D with an area of focus in physical design. Analyzed and debugged complex design challenges. Defined product requirement specifications. Guided implementation. Created test plan and performed beta testing. Designed, developed, and delivered training and marketing materials to field. ### Principle Hardware Engineer @ Oracle Corporation Jan 2013 – Jan 2014 | Santa Clara, CA EDA CAD tool development lead - Defined preliminary design concepts and worked with development team to implement them. Prioritize tasks among development teams. Tracked development schedule. Assisted in determining the best technical implementation methods. Performed as an AE to QA the tools. Developed deployment strategy. Setup and hosted training courses. Setup support protocols and mechanism. (With 1 granted US patent from this effort). ### Senior Hardware Engineer @ Oracle Corporation Jan 2010 – Jan 2013 | Santa Clara County, California, United States Developed high performance custom memories for various generations of SPARC processors - Refined micro architecture. Defined circuit spec and implemented it in schematic. - Used composition tools or worked with mask designers to compose layouts - Performed transistor level simulation and analysis. - Performed timing/power/area analysis, as well as various back-end analysis such as noise, signal EM, power EM/IR, clock tuning, etc Defined design methodologies with project leads and propagated design guidelines to design teams - Cell-based design methodology for timing and physical composition - Row decoder design methodology - Physical design layout methodology Developed and maintained several common and specialty cell libraries - Understood cell-based design methodology requirements - Developed and maintained common cells - Performed cell characterization for timing and power - Performed library QA and release process, logistic and record keeping ### Circuit Design Engineer @ Sun Microsystems Jan 2008 – Jan 2010 | Santa Clara, CA ### IC Design Intern @ Xilinx Jan 2007 – Jan 2007 • Developed a SEU verification flow including fault injectable cells replacement, test bench generation, and integration with existing test bench setup (in Perl) • Participated in standard cell library development • Characterized a newly developed configuration memory cell design • Designed the address line driver for the configuration memory ### Research Staff @ University of Washington Jan 2005 – Jan 2006 • Developed four design automation CAD tools (in PERL) for Locally-Clocked Dynamic Logic (LCDL, an asynchronous micropipeline technique) - LCDL design sizing and levelizing tool (a tool that pipelines static CMOS designs into LCDL asynchronous micropipeline designs) - Automatic cell generation tool - Level-by-level layout assignment tool - Post layout level-by-level timing verification tool • Characterized cells used in LCDL design flow by using NanoChar (Synopsys). Created Verilog models with timing information for all five LCDL designs • Designed and taped-out a low-power 168K bit ECC SRAM with the new Multi-Hamming Code Scheme in IBM 90 nm Technology. The new ECC scheme features multi-bit error detection and multi-bit (100%) error correction within each word • Designed and constructed pad frame with multiplexing circuitry to share I/O pads among five EDAC radiation-hardened memory designs in IBM 0.13um Technology • Designed two four-layer FR4 printed circuit boards (PCBs) for the radiation-hardened by design tapeout. One board features a radiation island, which allows the users to measure the current of the DUT caused by the radiation environment. Another board was designed for basic functionality test • Tested a 256K bit EDAC Self-Scrubbing SRAM under simulated radiation space environment at 88-Inch Cyclotron Laboratory in Lawrence Berkeley National Lab ## Education ### MS in Electrical Engineering Stanford University Jan 2006 – Jan 2008 ### BS in Electrical Engineering University of Washington Jan 2002 – Jan 2005 ## Contact & Social - LinkedIn: https://www.linkedin.com/in/jimmy-h-lin --- Source: https://flows.cv/jimmylin JSON Resume: https://flows.cv/jimmylin/resume.json Last updated: 2026-04-07