# JONGOCK OH

> 20+ Yr Veteran in Physical Design & IC Timing Closure (DTV/Automotive) | DTCO Lead for 3nm/1nm Next-Gen Process Enablement | 60+ Tape-outs (20 as Leader) | Synopsys US . Samsung Electronics Alumni

Location: Sunnyvale, California, United States
Profile: https://flows.cv/jongock

Physical Design with 20 years of experience in Samsung Electronics. Designed timing driven layout of DTV/Automotive integrated circuits with emphasis on timing closure. Performed place and route of digital IC's and large super blocks using state of the CAD tools. Expertise in Cadence P&R Flow and completed Olympus-SoC evaluation and Tape-out. Experienced with tape-out totally 60 projects in Samsung, out of them successfully tape-out 20 projects as a Leader. 

Subsequently, I transitioned to Synopsys, where for six years, I perform DTCO (Design-Technology Co-Optimization) work for Samsung LSI on the 3nm process, and enable early DTCO for Samsung Foundry on the 1nm process, including making design methodologies, flow automation, and validating new features in Synopsys US.

## Work Experience
### Principle Engineer @ Synopsys Inc
Jan 2019 – Present | 샌프란시스코 만 지역
Foundry PPA

### Principal Physical Deisgn Engineer @ Samsung Electronics
Jan 2000 – Jan 2019 | Korea
Foundry Design Service Team


## Education
### B.S. in Electrical and Electronics Engineering
Cheongju University


## Contact & Social
- LinkedIn: https://linkedin.com/in/jong-ock-oh-0628847a

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Source: https://flows.cv/jongock
JSON Resume: https://flows.cv/jongock/resume.json
Last updated: 2026-04-12