Architected a fully adaptive 5-tap analog Traveling-Wave FFE (TWFFE) equalizer for 106Gb/s PAM4 application in ST microelectronic HBT process:

• Even though this class of equalizer is not compatible with the LMS adaptation, modified it such that it was using the LMS engine on-chip

• Through analysis and circuit simulation found out that the TWFFE has superior noise performance compared to FFE

• Through analysis and simulation found out that the TWFFE suffers from the common-mode oscillation problem and found ways to alleviate this problem

• Came up with two layout versions of the TWFFE; a circular one and a rectangular one

• Extracted both versions of the delay-line, inductors and corresponding interconnects for s-parameters

models

• Ran simulations using the s-parameter models for the tap-delay, the overall insertion-loss and the

return-loss of the delay-line

Architected a fully adaptive 3-tap analog FFE equalizer for 56Gb/s PAM4 application in ST microelectronic

HBT process:

• The equalizer contained analog LMS engine on-chip

• The equalizer was used for both optical as well as electrical channels

• Tested and verified the equalizer on silicon

• Sampled the receiver (equalizer plus CDR) to customers

• Provided guidance for the Product Engineering regarding the production issues

Architected an FFE/DFE equalizer for electronic dispersion compensation of parallel optics applications at 25.78Gb/s NRZ in ST microelectronic HBT process:

• Firmware adaptation engine was used

• Tested and verified the equalizer on silicon

• A module containing this part was demonstrated at a trade show

• Architected a fully adaptive FFE/DFE receiver for 10GBASE-KR application in TSMC’s 40nmLP process

• Designed the circuitry for the analog portion of the 10GBASE-KR

• Tested and verified the 10GBASE-KR front-end on silicon

• Ported the entire 10GBASE-KR architecture into TSMC’s 28nmHP process

• Re-architecting the 10GBASE-KR front-end into a stand-alone product

• Verified the above front-end functionality for 25Gb/s applications

• Interfaced with potential IP customers

• Did system-level verification of the 4-lane RX/TX SERDES

• Ported multi-speed (1.25-to-10.3125Gb/s) RX/TX 4-lane SERDES IP into TSMC’s 40nm process with 7X2R

and 6X2Z metal stacks

• Modified the IP to work with customer’s legacy backplane channel

• Modified the IP by incorporating offset cancellation loop in the RX path

• Developed a rigorous approach for verifying the IP containing 0.5 million transistors

• Provided customer with guide-lines for SERDES IP integration

Raised $4.5 million Series A funding and was heavily involved in the following fund-raising rounds

• Hired executives and most of the employees of the company through rigorous interview process

• Architected and developed the 10GBASE-T chip from concept to implementation in IBM’s 65nm CMOS

• Specified and designed several building blocks of the chip

• Member of IEEE 802.3ae/802.3an standards committees

• Received special award for being a major contributor to IEEE 802.3an development work

• Invented, patented and implemented clock-less analog echo cancellers and analog line equalizers by using analog version of the LMS algorithm for adaptively training the analog tap weights in TSMCs 0.13m and

IBM’s 65nm processes

Co-founded and managed the company from its inception

• Handled all contracts, customer interfaces, technical management, marketing, business development and

human resource (recruiting, reviews etc.)

• Interfaced with outside payroll and legal personnel

• As the Lead Designer, developed the following VLSI Mixed-Signal ICs:

• Two generations of Analog Base-Band chips for CDMA/AMPS wireless cellular phones (0.8m & 0.6m CMOS) for 2.7-to-5.5V range operation

• Multiple foundry (TSMC, WSMC and ATMEL) versions of a 10/100BASE-T PHY for data communication having one of the industry’s lowest power consumptions, using 0.35m CMOS

• A 16-bit - CODEC for digital Audio application using 0.35m digital CMOS process

• A family of power-management ICs for PC lap-top and automotive applications

Managed the Voice/Data Design group consisting of nine (9) Mixed-Signal IC Designers working on various projects with emphasis on wireless as follows:

• A Low-Voltage low-power Analog Front End (AFE) including 16-bit - voice CODEC for DECT cordless applications which was NSC’s 1st 2.7V mixed-signal design in 0.8m 5V CMOS

• A 20-bit - ADC converter for Audio/Instrumentation applications using 0.8m CMOS

• An AFE for low-end FAX modem applications

• An AFE for CDMA cellular phone applications

• A feasibility study for high-speed high-resolution converters for Asymmetric Digital Subscriber Line

(ADSL) applications

Developed a mixed-signal methodology for Voice/Data design group in order to reduce cycle-time and assure

1st Silicon functionality