Computer Systems Laboratory (Zhang Group)
• Researched alternative front-end (using ANTLR) for a compiler that generates RISC-V processors in chisel HDL
• Ported a cache system from verilog to system verilog inside a chisel block-box
• Helped integrate the cache system into the RISC-V processors generated by the compiler
• Worked on the CPU/executable back-end for a compiler that compiles a pythonic DSL to heterogeneous architectures