Expertise in Low Power for Mobile SOC

Leading Power Grid implementation/Verification/Closure : Impacting PPA

Drive Low power expertise: Lead power saving strategies directly impacting PPA

Leading Low power verification efforts: power aware functional verification and multi voltage rule check post physical design : MVRC/VSILP/VCLP

Drive Signoff activities for Implementation and low power verification

Lead Power Grid Design and Analysis : To meet DRC and IR Drop for block level and chip level. Various Strategies to effectively use metal resource for Power Grid to get best PPA for Design in lower technology nodes

Spice and sta correlation for lower technology nodes

Chip Level and Block Level netlist to signoff expertise

Lead Power Shut off implementation : Evaluate/Analyze various Power Shut off methodology. Decision making on which works best for the designs. Drive infrastructure to deploy it across various Designs within Company.

Lead Top Level of a Hierarchical design and block closure methodology. Drive IP integration planning/implementation/Signoff reviews. Padding Planning and SSO analysis for a given package based on Ldi/dt using Spice Simulations.

Lead overall PnR methodology and tool evaluations for effective and faster design closures.

Developed an PT-ICC integrated flow for effective pipeline location identification and insertion on physical design eco generation. Widely used across multiple designs.

Closure of a complex design with 250+ macros. Tighter loop with RTL Designer and multiple floorpan experiment for congestion and timing closure. In parallel worked on cross tool flows to get through various Pnr Stages with best results. Tune the rtl/netlist/floorplan/pnr recipes stable.

Manage a design, driving weekly customer updates and internal cross functional meetings. Schedule planning from synthesis to tapeout including the best possible package selection within given budget meeting deaign requirements.

Lead the 1st Flip Chip Hierarchical Design at Open Silicon : Driven various decisions for flow/package/Blockfloorplanning/IOplacement at various stage of project milestone.

Drive customer meetings at various stages of project.

Got coached for design management position for future projects.

Work closely with block owners and own top level floor planning and implementation.

Work on feedthrough planning and insertion with Front End Team forming closure of critical DDR interface to various clients accessing memory through DDR controller

Bump planning and RDL routing planning

Lead Automation tasks that were used across board for multiple designs from adoring automation to power grid to IP integration.

Spice SSO Analysis for different packages from Wirebond/CSP/FlipChip/WirebondLead/WirebondPin packages.

IR/EM closure for various chip through efficient power planning for wire bond chips. Develop IR and EM flows and methodology.

Presented Papers at Magma Tool Forum and won 2nd prize.