# Kapil Kothari > SOC Physical Design Leadership | Brewing IdeasπŸ’‘ @ Apple Location: Cupertino, California, United States Profile: https://flows.cv/kapilkothari Leadership Skill Set: Lead and Manage design from initial design exploration phase to tapeout at design service setup and in-house design at product company setup. Managing central team with cross functional impact, influencing decision making in cross functional meetings. Driving technology evaluation maximizing PPA. Managing fullchip flat wirebond and hierarchical flip chip socs from netlist to tapeout, partnering with packaging team on package selection. Benefit and Cost analysis/mitigation during design phases. Technical Skill Set: Block Level and Chip Level implementation expertise. PPA optimization for deep sub micron technologies. Power Grid/IR EM Flow/Voltage Drop budgeting. Low Power Strategies for Low power implementation. Knowledge of package types and package implications on overall product. ## Work Experience ### Sr Manager Silicon Engineering and Soc powergrid and low power architect @ Apple Jan 2011 – Present | Cupertino, CA Expertise in Low Power for Mobile SOC Leading Power Grid implementation/Verification/Closure : Impacting PPA Drive Low power expertise: Lead power saving strategies directly impacting PPA Leading Low power verification efforts: power aware functional verification and multi voltage rule check post physical design : MVRC/VSILP/VCLP Drive Signoff activities for Implementation and low power verification Lead Power Grid Design and Analysis : To meet DRC and IR Drop for block level and chip level. Various Strategies to effectively use metal resource for Power Grid to get best PPA for Design in lower technology nodes Spice and sta correlation for lower technology nodes Chip Level and Block Level netlist to signoff expertise ### Lead Physical Design @ Sigma Designs Jan 2010 – Jan 2011 Lead Power Shut off implementation : Evaluate/Analyze various Power Shut off methodology. Decision making on which works best for the designs. Drive infrastructure to deploy it across various Designs within Company. Lead Top Level of a Hierarchical design and block closure methodology. Drive IP integration planning/implementation/Signoff reviews. Padding Planning and SSO analysis for a given package based on Ldi/dt using Spice Simulations. Lead overall PnR methodology and tool evaluations for effective and faster design closures. ### Member of Technical Staff @ Juniper Networks, Sunnyvale Jan 2009 – Jan 2010 Developed an PT-ICC integrated flow for effective pipeline location identification and insertion on physical design eco generation. Widely used across multiple designs. ### Senior Design Engineer San Diego @ Qthink Jan 2008 – Jan 2009 Closure of a complex design with 250+ macros. Tighter loop with RTL Designer and multiple floorpan experiment for congestion and timing closure. In parallel worked on cross tool flows to get through various Pnr Stages with best results. Tune the rtl/netlist/floorplan/pnr recipes stable. ### Design Manager @ Open-Silicon, Inc. Jan 2005 – Jan 2008 Manage a design, driving weekly customer updates and internal cross functional meetings. Schedule planning from synthesis to tapeout including the best possible package selection within given budget meeting deaign requirements. Lead the 1st Flip Chip Hierarchical Design at Open Silicon : Driven various decisions for flow/package/Blockfloorplanning/IOplacement at various stage of project milestone. Drive customer meetings at various stages of project. Got coached for design management position for future projects. Work closely with block owners and own top level floor planning and implementation. Work on feedthrough planning and insertion with Front End Team forming closure of critical DDR interface to various clients accessing memory through DDR controller Bump planning and RDL routing planning Lead Automation tasks that were used across board for multiple designs from adoring automation to power grid to IP integration. Spice SSO Analysis for different packages from Wirebond/CSP/FlipChip/WirebondLead/WirebondPin packages. IR/EM closure for various chip through efficient power planning for wire bond chips. Develop IR and EM flows and methodology. Presented Papers at Magma Tool Forum and won 2nd prize. ### Hardware Engineer @ Cisco Systems Jan 2002 – Jan 2005 Started my 1st Industry experience at Cisco under very strong management and technical leaders who guided me through the knowhow of physical design of blocks, full chip perspective and package perspective. Full Chip IR EM Exposure. Power Estimation of standard cells sing Spice and Macro Power Estimation by developing scaling factors. Thanks to @Abhijit Dutta/Venkat Ghanta/Vivek Tatke for giving me a good guidance motivation and start in physical design field. ## Education ### Masterts of Technology in Microelectronics Indian Institute of Technology, Bombay ### Certificate in Leadership Training for managers Dale Carnegie Training ### B.E in Instrumentation University of Mumbai ### Diploma in Instrumentation Vivekanand Institute of Technology ## Contact & Social - LinkedIn: https://linkedin.com/in/kapil-kothari-b918b61 --- Source: https://flows.cv/kapilkothari JSON Resume: https://flows.cv/kapilkothari/resume.json Last updated: 2026-04-13