As a key member of the software team developing a complete RTL-to-bitstream FPGA CAD flow

Developed methodology and CAD tools for IC design verification

Analyzed design flow; evaluate and integrate commercial tools (including Cadence and Synopsys) for design automation

Working knowledge of Python, Perl, TCL, Verilog, C/C++, Spice, Skill, Matlab, and hardware architectures of Cyclone and Stratix products

Coordinated cross-functional projects that involve design, test, softwares, and design automation departments

Highlight projects include:

1. Data Management Project: Coordinated the effort among multiple teams from CAD, IC design, software, and testing organizations to build the infrastructure for our next generation Perforce-based database management system that suit the needs across different organizations

2. Full-Chip Connectivity Verification: Provided a Skill plug-in for our designers to do path-tracing in full-chip level. The tool also handle verification for our programmable bits, which is unique to FPGAs.

3. Schematic Design Rule Checks: Built a C/C++ utilities using Open Access and Qt. The program can be plug-in to Virtuoso,so the cross-probing can be achieved between Virtuoso and our check system. Our in-house waiver system give our design managers the power to regulate and monitor the waivers used across teams.

• Developed clock placement CAD tools for the ProASIC3 and Fusion FPGA products

• Working knowledge of object-oriented programming, C++, Verilog, VHDL, and FPGA architectures

• Experienced in product development and system testing for EDA software under tight schedule

Served as a field specialist in Brampton, Ontario, Canada and developed the Operations and Control Software (OCS), the control system used on CanadArm2, the robotic arm on the International Space Station (ISS).