# Kara P. > Software Engineer Location: San Jose, California, United States Profile: https://flows.cv/karap Goals: • Constantly looking for challenging projects that fit my professional interest and flexible schedule Professional Experience Technical • Strong coding and algorithm development skills • Knowledgeable in CAD tools, IC design methodology, and FPGA architectures Project Management • Proven track record to lead multiple initiatives, track progress, organize meetings in a dynamic environment Technical Support and Training • A team player and an outstanding motivator in a multi-disciplinary team setting Effective Communicator • Technical presentations, public speaking, strong inter-personal skills • Fluently communicate and write in English and Chinese Other Organization Experience • Organize weekend events for toddlers and working parents in South Bay Area ## Work Experience ### Software Engineer @ Efinix, Inc. Jan 2012 – Present As a key member of the software team developing a complete RTL-to-bitstream FPGA CAD flow ### Member of Technical Staff, Design Automation Engineer @ Altera Jan 2006 – Jan 2011 Developed methodology and CAD tools for IC design verification Analyzed design flow; evaluate and integrate commercial tools (including Cadence and Synopsys) for design automation Working knowledge of Python, Perl, TCL, Verilog, C/C++, Spice, Skill, Matlab, and hardware architectures of Cyclone and Stratix products Coordinated cross-functional projects that involve design, test, softwares, and design automation departments Highlight projects include: 1. Data Management Project: Coordinated the effort among multiple teams from CAD, IC design, software, and testing organizations to build the infrastructure for our next generation Perforce-based database management system that suit the needs across different organizations 2. Full-Chip Connectivity Verification: Provided a Skill plug-in for our designers to do path-tracing in full-chip level. The tool also handle verification for our programmable bits, which is unique to FPGAs. 3. Schematic Design Rule Checks: Built a C/C++ utilities using Open Access and Qt. The program can be plug-in to Virtuoso,so the cross-probing can be achieved between Virtuoso and our check system. Our in-house waiver system give our design managers the power to regulate and monitor the waivers used across teams. ### Senior Software Engineer @ Actel Jan 2003 – Jan 2006 - Developed clock placement CAD tools for the ProASIC3 and Fusion FPGA products - Working knowledge of object-oriented programming, C++, Verilog, VHDL, and FPGA architectures - Experienced in product development and system testing for EDA software under tight schedule ### Graduate Student @ The University of British Columbia Jan 2000 – Jan 2002 ### Field Engineer and Software Engineer @ MacDonald Dettwiler and Associates Limited Jan 1999 – Jan 2000 | Richmond, BC, Canada Served as a field specialist in Brampton, Ontario, Canada and developed the Operations and Control Software (OCS), the control system used on CanadArm2, the robotic arm on the International Space Station (ISS). ## Education ### Master in Electrical and Computer Engineering The University of British Columbia ## Contact & Social - LinkedIn: https://linkedin.com/in/kara-p-4322221 - Portfolio: http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/Committee.html - Portfolio: http://www.meetup.com/South-Bay-Working-Moms-of-Tots/ --- Source: https://flows.cv/karap JSON Resume: https://flows.cv/karap/resume.json Last updated: 2026-04-10