• Architected and deployed production-grade AMS EDA frameworks for schematic and layout automation across advanced-node silicon programs.

• Designed scalable CAD architectures and methodologies enabling reusable flows for next-generation semiconductor technologies.

• Developed custom algorithm-driven EDA tools improving layout efficiency, verification robustness, and first-pass design success.

• Automated high-complexity AMS workflows, eliminating manual bottlenecks and significantly reducing design cycle time.

• Led end-to-end software development using Python, SKILL/SKILL++, and Tcl, from architecture through global deployment.

• Integrated automation across design, verification, and validation teams, ensuring alignment with silicon quality and manufacturability goals.

• Drove continuous evolution of internal EDA infrastructure, including regression frameworks, CI/CD pipelines, and workflow scalability.

Engineered custom EDA tools to automate complex analog layout tasks, serving as the primary technical authority for analog layout project methodologies.

• Architected and owned AMS EDA automation frameworks supporting analog IP development.

• Designed layout-centric methodologies and tool ecosystems that improved first-pass success, verification robustness, and IP quality.

• Oversaw AMS layout automation delivery, ensuring scalability, production readiness, and compliance with internal quality standards.

• Led layout team and memory SRAM projects, providing technical guidance and hands-on support for analog and mixed-signal layout design flows.

• Developed and optimized EDA flows and tools including extraction flows, porting utilities, and layout automation scripts, improving designer productivity.

• Configured and maintained layout and schematic verification setups, including editors, Sync utilities, memory compilers, DRC/LVS, and EMIR tools.

• Collaborated with software teams to enhance and integrate EDA tools into internal design flows.

• Created and implemented methodologies for new technologies, supporting advanced-node memory and logic library layouts.

• Provided CAD support and training for local layout teams, ensuring adoption of tools and best practices.

• Coordinated with foundries and customers to validate flows and support project delivery.

• Designed and verified SRAM, ROM, and CAMRAM embedded memories for advanced nodes, ensuring high-quality layouts and adherence to design rules.

• Led layout projects, independently solving highly complex design challenges requiring advanced evaluation of multiple design factors.

• Applied innovative methods and techniques to optimize layout and verification processes, directly impacting product success and technology development.

• Exercised independent judgment in developing evaluation criteria and solutions for challenging layout problems.