# Karen Ayvazyan > PhD | Principal EDA Software Engineer / CAD | Analog IC Layout & Design Automation | Cadence Virtuoso SKILL | Python & AI/ML for EDA Automation | Tool Architecture & Methodology Location: Cupertino, California, United States Profile: https://flows.cv/karenayvazyan I am a Principal EDA Software Engineer with 18+ years of experience bridging silicon physics and software engineering with a unique combination of AMS layout/design, CAD flows, methodology, and automation expertise. I specialize in architecting, developing, and deploying production-grade EDA tools that transform complex Analog/Mixed-Signal (AMS) design challenges into scalable, high-efficiency automation. My expertise spans the full research-to-production lifecycle: from algorithm design and architecture to CI/CD integration and global deployment. I focus on identifying structural inefficiencies in design flows and delivering robust, scalable solutions that reduce design cycles, improve quality, and maximize silicon yield. Core Technical DNA • CAD Automation: Expert-level Cadence Virtuoso SKILL/SKILL++, Python, Tcl, Shell; CAD flow development for AMS layout/design • Design Expertise: Deep knowledge of AMS layout/design for CMOS, FinFET, and GAA architectures across nodes from 65nm down to 4nm and beyond (TSMC, Samsung, GF, IBM, ST, UMC) • AI/ML for EDA: GNN-based parasitic estimation; regression models for area/effort prediction; applied Generative AI for verification, documentation and test automation • Physical Design & Verification: LVS, DRC, ERC, DFM, ANT; EM/IR analysis, self-heating, R/C extraction, and device matching • Software Engineering: Algorithm architecture (graph theory, combinatorial optimization, geometry), GUI development, and Python packaging Representative Production-Grade Solutions • Intelligent RC-Aware Router: Developed a parasitic-driven AMS router delivering results comparable to expert manual routing • Node Migration Suite: Built a fully automated schematic and layout porting system, saving 50+ man-years of manual effort across technology nodes • ML-Driven Predictors: Architected pre-layout parasitic estimation and design complexity analyzers to bridge the pre-to-post layout gap • Template-Based Generators: Created technology-independent frameworks for rapid IP creation, layout prototyping, and ring oscillator generation • Design Analyzer Suite: Developed tools for schematic topology extraction, signal tracing, and automated GDS/LEF/Netlist processing LAYOUT/SCHEMATIC EDITORS: Cadence Virtuoso, Synopsys Custom Compiler/Designer VERIFICATION TOOLS: Mentor Calibre, Synopsys IC Validation REVISION CONTROL: SOS, P4, Design Sync, Git, SVN, IC Manage FOUNDRIES: TSMC, Samsung, GF, IBM, ST, UMC NODES: … 3nm, 4nm, 5nm, 7nm, 8nm, 10nm, 14nm, 16nm, 20nm, 28nm, 32nm, 45nm, 65nm DESIGNS: SRAM memories, Logic libraries, Sensors, Serdes ## Work Experience ### Principal EDA Software Engineer | AMS Automation Architect | Physical Design @ Apple Jan 2021 – Present • Architected and deployed production-grade AMS EDA frameworks for schematic and layout automation across advanced-node silicon programs. • Designed scalable CAD architectures and methodologies enabling reusable flows for next-generation semiconductor technologies. • Developed custom algorithm-driven EDA tools improving layout efficiency, verification robustness, and first-pass design success. • Automated high-complexity AMS workflows, eliminating manual bottlenecks and significantly reducing design cycle time. • Led end-to-end software development using Python, SKILL/SKILL++, and Tcl, from architecture through global deployment. • Integrated automation across design, verification, and validation teams, ensuring alignment with silicon quality and manufacturability goals. • Drove continuous evolution of internal EDA infrastructure, including regression frameworks, CI/CD pipelines, and workflow scalability. ### Principal Engineer @ Socionext Europe Jan 2020 – Jan 2021 | Frankfurt Am Main Area, Germany Engineered custom EDA tools to automate complex analog layout tasks, serving as the primary technical authority for analog layout project methodologies. ### Analog and Mixed Signals Methodology @ Qualcomm Jan 2018 – Jan 2020 | County Cork, Ireland • Architected and owned AMS EDA automation frameworks supporting analog IP development. • Designed layout-centric methodologies and tool ecosystems that improved first-pass success, verification robustness, and IP quality. • Oversaw AMS layout automation delivery, ensuring scalability, production readiness, and compliance with internal quality standards. ### R&D Senior Manager, Analog and Mixed Signals Layout Design @ Synopsys Jan 2012 – Jan 2018 • Led layout team and memory SRAM projects, providing technical guidance and hands-on support for analog and mixed-signal layout design flows. • Developed and optimized EDA flows and tools including extraction flows, porting utilities, and layout automation scripts, improving designer productivity. • Configured and maintained layout and schematic verification setups, including editors, Sync utilities, memory compilers, DRC/LVS, and EMIR tools. • Collaborated with software teams to enhance and integrate EDA tools into internal design flows. • Created and implemented methodologies for new technologies, supporting advanced-node memory and logic library layouts. • Provided CAD support and training for local layout teams, ensuring adoption of tools and best practices. • Coordinated with foundries and customers to validate flows and support project delivery. ### R&D Senior II, Embedded Memories Layout Design @ Synopsys Jan 2008 – Jan 2012 • Designed and verified SRAM, ROM, and CAMRAM embedded memories for advanced nodes, ensuring high-quality layouts and adherence to design rules. • Led layout projects, independently solving highly complex design challenges requiring advanced evaluation of multiple design factors. • Applied innovative methods and techniques to optimize layout and verification processes, directly impacting product success and technology development. • Exercised independent judgment in developing evaluation criteria and solutions for challenging layout problems. ### Engineer @ ViaSphere Technopark Co. Jan 2007 – Jan 2008 Internship in the laboratory of semiconductor materials and devices ## Education ### Doctor of Philosophy (Ph.D) in Engineering in Management, Automation and Electronic State Engineering University of Armenia ### Master's degree in VLSI design engineer State Engineering University of Armenia ## Contact & Social - LinkedIn: https://linkedin.com/in/karen-ayvazyan-a66b155b --- Source: https://flows.cv/karenayvazyan JSON Resume: https://flows.cv/karenayvazyan/resume.json Last updated: 2026-04-12