Technical lead with broad technical background in Custom/ASIC IC design and FPGA architecture. Career and experience focused on DRAM/High Bandwidth Memory/LVDS/SerDes Physical Layer (PHY) IP design. Horizontal focus on IP power modeling methodologies.
Experience
2022 — Now
2021 — 2022
2016 — 2022
2019 — 2021
2014 — 2016
Education
Universiti Teknologi Malaysia