DDR PHY IP design

IO Subsystem / DDR PHY design for Intel Programmable Solution Group

Technical lead in High Bandwidth Memory (HBM) and DDR Physical Layer (PHY) IP design for FPGA product.

Involved in full development cycle from exploration/definition, design entry/coding, design modeling/simulation flow definition/automation to post-silicon check-out/bring-up/debug.

Issued US patent: #8723575, #8816743, #9077514

DesignWare DDR PHY IP Design.

IP Frontend Lead for LPDDR5 DesignWare DDR PHY IP design

Technical lead in power modeling and optimization for FPGA product - involved in full development cycle from exploration, design modeling/simulation flow definition & automation to post-silicon check-out/bring-up/debug.

Previously lead and managed team in IO/DDR physical layer (PHY) design.