# Kin Hong Au

> DDR PHY / IO Subsystem IP design

Location: San Jose, California, United States
Profile: https://flows.cv/kinhongau

Technical lead with broad technical background in Custom/ASIC IC design and FPGA architecture. Career and experience focused on DRAM/High Bandwidth Memory/LVDS/SerDes Physical Layer (PHY) IP design. Horizontal focus on IP power modeling methodologies. 

Issued US patent:
#8723575, #8816743, #9077514

Experienced with various Custom/ASIC design flow/methodologies: Custom Schematic design/optimization, SPICE based simulation/verification, logic/RTL design/verification, synthesis, static timing analysis (STA), power simulation/modeling.

## Work Experience
### Silicon Design Engineer @ AMD
Jan 2022 – Present
DDR PHY IP design

### SoC Design Engineer @ Intel Corporation
Jan 2021 – Jan 2022 | San Jose, California, United States
IO Subsystem / DDR PHY design for Intel Programmable Solution Group

### SoC Design Engineer @ Intel Corporation
Jan 2016 – Jan 2022 | San Jose, California
Technical lead in High Bandwidth Memory (HBM) and DDR Physical Layer (PHY) IP design for FPGA product.
Involved in full development cycle from exploration/definition, design entry/coding, design modeling/simulation flow definition/automation to post-silicon check-out/bring-up/debug.

Issued US patent: #8723575, #8816743, #9077514

### ASIC Digital Design Engineer @ Synopsys Inc
Jan 2019 – Jan 2021 | Mountain View, California
DesignWare DDR PHY IP Design.
IP Frontend Lead for LPDDR5 DesignWare DDR PHY IP design

### Senior Staff IC Design Engineer @ Altera
Jan 2014 – Jan 2016 | Penang, Malaysia
Technical lead in power modeling and optimization for FPGA product - involved in full development cycle from exploration, design modeling/simulation flow definition & automation to post-silicon check-out/bring-up/debug.

Previously lead and managed team in IO/DDR physical layer (PHY) design.

### IC Design Manager @ Altera
Jan 2013 – Jan 2014 | Penang, Malaysia
Design high-speed DDR physical layer (PHY) IP for FPGA/Structured ASIC product.
Involved in full development cycle - research/exploration, architecture specification/definition, design modeling, custom/ASIC circuit implementation/verification, physical design/layout planning, and post-silicon check-out/bring-up/debug.

### IC Design Section Head @ Altera
Jan 2012 – Jan 2013
Design high-speed DDR physical layer (PHY) IP for FPGA/Structured ASIC product.
Involved in full development cycle - research/exploration, architecture specification/definition, design modeling, custom/ASIC circuit implementation/verification, physical design/layout planning, and post-silicon check-out/bring-up/debug.

### Staff IC Design Engineer @ Altera
Jan 2011 – Jan 2012
Design high-speed DDR physical layer (PHY) IP for FPGA/Structured ASIC product.
Involved in full development cycle - research/exploration, architecture specification/definition, design modeling, custom/ASIC circuit implementation/verification, physical design/layout planning, and post-silicon check-out/bring-up/debug.

### Senior IC Design Engineer @ Altera
Jan 2009 – Jan 2011

### Advanced IC Design Engineer @ Altera
Jan 2007 – Jan 2009

### IC Design Engineer @ Altera
Jan 2005 – Jan 2007

### Intern @ Intel Corporation
Jan 2004 – Jan 2004
Scripting and design automation for RTL design compilation and revision control


## Education
### BSc in Electronics Engineering
Universiti Teknologi Malaysia


## Contact & Social
- LinkedIn: https://linkedin.com/in/kin-hong-au

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Source: https://flows.cv/kinhongau
JSON Resume: https://flows.cv/kinhongau/resume.json
Last updated: 2026-04-13