Responsibility: Pegasus Tool Validation

• Worked on Pegasus Physical Verification System Fill batch flow validation.

• Worked on Virtuoso iPegasus GUI fill flow integration/validation.

• Tested functionality of various Density(DFM) and Fill Pegasus tool commands and options and reported issues to R&D Engineers.

• Validated and created test scenarios for enhancement Fill/DFM features as requested by various customers.

• Worked for multiple customers and foundries(3nm-28nm)

• Knowledge of DRC and Dummy Rule decks written in Physical verification Language(PVL).Can create custom rule decks.

• Carried out Performance and Regression testing.

• Was part of global team collaborating across US, Ireland, Taiwan, India and Shanghai.

Physical Verification Engineer of 10nm SOCs and IPs in Intel's XPG.

• Worked on DRC, LVS, Density, Antenna violations and other physical verification flows in several complex partitions with multi-million gate count until signoff closure.

• Implemented Timing Closure ECOs (set up, hold, max trans, max cap), Functional ECOs such as Buffer Insertions ,Logic Gate Insertions, Complex logical ECOs, RV,EM,IR and crosstalk violation fixes ,Net improvements, upsize/downsize cells,etc.

• Was part of a 5 member team from Intel SDG leading to the closure of 70+ partitions critical to “Icelake Processor” handled at client development center & driven until tape-in.

• Well versed with Tcl scripting to fix huge DRC and Density violations.

• Knowledge of partition level SDBUILD (ICC2 synthesis and APR2 flows) Intel HDK flows.

• Trained in Physical Design and performed Floorplanning to Timing Signoff at block level in 28nm node using Synopsys ICC2,STAR RC and PrimeTime.

• Knowledge of Python and Perl scripting.