Led Digital Design Methodology & Flow development on advanced process nodes. Transformed team of 60+ engineers into a high performing unit through reorganization, improved operations. Doubled innovation output and streamlined customer support. Enabled transformation of team from a single platform to a segment specific (Mobile, HPC, Automotive, ULV) platform solution provider.

Established the ASIC Design Solutions team and grew it organically to a team of 65 engineers. Defined and implemented all operational aspects including response to customer RFQs, benchmarking for customer acquisition, design & signoff review, methodology definition, training, and COT customer support. Design Manager for Physical Design Implementation of reticle limiting 22nm networking chip, complex testchips for critical customer IPs resulting in first-time successful Silicon.

PDT lead for the High Performance Computing Group, responsible for ensuring microprocessor ecosystem readiness. Implementation lead for two clusters on the microprocessor design team.

Design manager on the Intel (R) Core i7 microprocessor responsible for design and implementation of the memory controller unit. Led a team of 20+ engineers and mask designers to deliver micro-architecture, logic, and physical implementation of the memory controller. Also led logic verification and design methodology for the Uncore cluster.