# Lalit Garg

> Principal Engineer & Engineering Leader | Silicon Platform Execution & Cross Functional Ownership | Advanced-Node CPU & SoC Platforms  | Global Teams | Power, EM/IR, Signoff

Location: San Jose, California, United States
Profile: https://flows.cv/lalit

I am a principal-level silicon engineering and product engineering leader with 20+ years of experience driving execution of advanced-node CPU and SoC platforms from methodology definition through signoff and production readiness.

My work spans power, EM/IR, thermal, and ESD signoff across digital and analog designs, with deep hands-on experience enabling N3 / N5 / N7 / 3nm / 2nm technology nodes and 3D-IC flows. I have led cross-functional efforts across design, physical implementation, signoff, vendors, and foundries to deliver tapeout-critical capabilities under aggressive schedules.

I have built, scaled, and led high-performing global teams across the US and Asia, defining operating models, quality frameworks, and deployment strategies for complex silicon platforms and EDA software. My experience includes vendor selection and management, foundry certification and qualification, and direct engagement with executive stakeholders and key customers.

I enjoy working at the intersection of deep technology, execution discipline, and people leadership—turning complex, ambiguous problems into scalable, repeatable delivery frameworks.

## Work Experience
### Principal Engineer @ Qualcomm
Jan 2022 – Present | Santa Clara County, CA
Defined power grid and PDN signoff methodology and flows for next-generation CPU clusters (3nm/2nm), enabling consistent execution by multiple internal teams.

Led methodology deployment across US and India teams, PDN analysis and physical design engineers on standard practices and flows.

Directed vendor evaluation and engagement to ensure tooling supported project requirements and advanced-node process rules.

Partnered with internal stakeholders to identify risks, recommend mitigation strategies, and standardize signoff best practices, reducing potential tapeout issues.

### Product Engineering Director @ Cadence Design Systems
Jan 2016 – Jan 2022 | San Jose, CA
Built and scaled global product engineering teams (US, India, China, Taiwan, Korea) responsible for deployment, benchmarking, and customer enablement of Voltus platform.

Owned multi-generation product and deployment roadmap, aligning R&D, field, and strategic customers to deliver tapeout-critical signoff capabilities.

Served as primary executive interface for customers and foundries, managing escalations, certifications, and risk mitigation.

Drove methodology and flow adoption for N3/N5/N7/3DIC designs, resulting in improved first-pass signoff success and reduced design iterations.

### Sr Principal Product Engineer @ Cadence Design Systems
Jan 2000 – Jan 2016 | Noida
Built and scaled high-performing engineering teams across APAC to deploy Voltus EM/IR signoff methodologies at major semiconductor customers (Samsung, TSMC, TI, NXP, ARM, GlobalFoundries).

Led methodology definition, early adoption, and benchmarking, establishing processes that later supported global rollout and multi-generation programs.

Partnered with field and customer teams to standardize power, EM/IR, and thermal signoff practices, ensuring consistent, reliable design results.

Directed competitive evaluations and provided actionable feedback to R&D for tool enhancements and feature prioritization.

Achieved multiple foundry certifications (28/20/16nm) and enabled broader product adoption across customer portfolios.

### QA Engineer @ Tata Telecom Ltd
Jan 1999 – Jan 2000 | Gandhinagar
Validated PCB modules and system integration for EPABX and UHF/microwave radio platforms.

Supported end-to-end product testing, troubleshooting, and quality assurance for telecom hardware.


## Education
### Gujarat University


## Contact & Social
- LinkedIn: https://linkedin.com/in/lalit-garg-382a9a4

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Source: https://flows.cv/lalit
JSON Resume: https://flows.cv/lalit/resume.json
Last updated: 2026-04-12