Software Engineer, Place and Route (PnR) tech lead

ASIC Design Methodology & Flow Development(APR)

Implement and enhance the physical design tools, as part of the integrated CAD tool environment, for the next generation microprocessor designs with TSMC 40, 28, 20, 10 and 7 nanometer technologies.

Lead and architected clock network generation with extremely low skew, including fishbone/comb route, shielding, post-mesh clock header insertion and placement, etc.

Lead and architected special routers such as space router, mixing gridded and gridless router, power router, ECO router and build-in DRC checker;

Lead and architected physical synthesis features such as high fanout synthesis, buffer-guided route and on-route buffering.

Lead and architected buffer legalization.

Interact with design teams to define the methodology for CPU design with hybrid commercial EDA tools and in-house tools. Also have an opportunity to participate in a broad range of CAD tool development activities.

Participated Open Access Track Patterns working group(Si2, Altera, Cadence, IBM, Intel, Oracle, and Synopsys)

EDA software development

Analyze and solve complex problems in the tightly integrated design-driven IC layout tools.

Architecture and Algorithm design. Fundamental geometric algorithm library, automatic Layout Generation and editing.

Data Structure and database format Maintain for in-house database and some industry standard format such as GDS II and HSPICE.

GUI/Cross platform design, using cross-platform framework QT to create GUI application.