# Lloyd Ramseyer

> Hardware Engineer @ Cognichip | Lead developer of Vaporview

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/lloydramseyer

Hardware engineer and reluctant front end developer. Passionate about democratizing chip design. Preference towards using problems to develop people rather than using people to develop problems.

Ambitious and creative. Obsessions include minimizing friction, scalability, portability, and excellent data visualization. Building things from hack demo to customer ready product.

I aim to set and seek out positive and healthy culture in all spheres of life. I’m a firm believer that the biggest technical problems are ultimately people problems at the end of the day. No single person is capable of doing it all, so it’s crucial that we empower others who are on the journey with us.

Overview of experience:
Firmware development | Test Automation | Hardware Design Verification | GDDR6 Protocol | PCIe protocol | VScode Extension development | System level Linux | Bash Scripting | High-Speed Signal Processing | Optics | Aerospace

Technical Skills:
Languages: System Verilog | C/C++ | Typescript | Javascript | Ruby | Python | TCL | Perl | Matlab | Rust

Software/Tools: Git | Verdi | Solidworks | Fusion 360 | Adobe Photoshop

Hobbies include: running, biking, skiing, rock climbing, backpacking, photography, and music.

When contacting, please include the RTL to a 4 deep, 32 bit wide asynchronous FIFO written in System Verilog.

## Work Experience
### Staff Engineer @ Cognichip Inc.
Jan 2025 – Present | Redwood City, California, United States

### Senior Engineer @ Achronix Semiconductor Corporation
Jan 2021 – Jan 2025 | Santa Clara, California, United States
• Designed, wrote, and productized GDDR6 Phy training firmware and bitstream generation code for Speedster 7t1500
• Wrote GDDR6 test suite for Phy tuning
• Integrated IO ring (DDR4, PCIe, Ethernet SerDes) initialization and management into firmware
• Created firmware code base for verification testing

### Senior Hardware Design Verification Engineer @ Marvell Semiconductor
Jan 2018 – Jan 2021 | Santa Clara, California, United States
Hardware Verification Engineer
• Defining and maintaining hardware verification test cases using the UVM methodology in System Verilog for NVMe flash controller and NVMe switch products
• Debug hardware design and documentation issues with waveform capture tools
• Advise hardware designers on best practices from my experience as a firmware engineer

Customer Application Engineer - NVMe Accelerator
• Defined and maintained internal performance data collection and presentation methods for the NVMe switch product
• Designed and set up testing lab for performance testing and firmware debug
• Supported enterprise OEM and major hyperscale cloud customers in integration efforts

--Skills and Technologies
• System Verilog
• Python
• Perl
• Shell scripting
• PCIe protocol
• AXI protocol
• Hardware Verification
• Waveform Capture

### SoC Power Engineer @ NVIDIA
Jan 2017 – Jan 2017 | Santa Clara, CA
•	Measured performance and power on GPUs and SoCs across a wide range of benchmarks for many departments across the company.
•	Analyzed data in order to compare power usage and performance across hardware generation, software revision and competitor products. 
•	Wrote and maintained testing automation code in a Perl environment in order to increase team productivity and reduce potential for human error from manual testing
•	Improved data collection and processing methodologies, streamlining the workflow, and improving turnaround time for requests.
•	Defined configuration settings for Unix and Windows based test systems; writing shell and bat setup scripts.

--Skills:
• Perl
• Bash/Unix shell scripting
• Batch scripting

### HDD Channel Integration Engineer @ HGST, a Western Digital company
Jan 2013 – Jan 2016
Recording Subsystems - Recording Electronics
Read/Write Channel Integration Engineering
• Performed post-silicon hardware integration of HDD read/write data channels.
• Designed experiments for feature checkout, feature validation, firmware debug, and failure analysis.
• Used oscilloscopes and arbitrary waveform generators (AWGs) for low level debug
• Worked cross-functionally with program teams, firmware developers, vendors, and other integration teams.

--Skills:
• HDD Read/Write Channels
• High speed signal processing
• Signal Integrity
• Test Automation: TCL, Perl
• Hardware Debug/FA
• Hardware Bring up
• Generating Test Plans/Test Procedures
• A3 Thinking
• Hardware/Firmware bug tracking
• Firmware Writing: C++
• PCB Debug

### Electrical Engineering Intern @ ArcelorMittal
Jan 2012 – Jan 2012 | Burns Harbor, IN
Managed maintenance technician team within steel production that maintained equipment.

### SIT lab co-op @ HGST, a Western Digital company
Jan 2010 – Jan 2010
• Tested Hard Disk Drives (HDDs) and Solid State Drives (SSDs) at the device level
• Tested power usage of HDDs and SSDs in various workload conditions
• Stress tested HDDs and SSDs under varying thermal, power, noise, and ESD conditions to ensure the drives meet customer specifications

--Skills:
• RAID and JBOD arrays
• MatLab
• Generating Test Procedures: TCL, LabView
• Device Debug/FA


## Education
### BS in Electrical Engineering
Michigan Technological University


## Contact & Social
- LinkedIn: https://linkedin.com/in/lramseyer

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Source: https://flows.cv/lloydramseyer
JSON Resume: https://flows.cv/lloydramseyer/resume.json
Last updated: 2026-04-01