Led team of 8, mentored 25+ diverse engineers, and delivered a complex mixed-signal memory PHY design (8+ mm^2, 200K sequentials) to multiple SoC customers.
● Delivered new IP, with zero functional bugs, directly to first product silicon.
● Achieved IP bring-up in 12 hours using a brand new link training solution.
● Reduced peak power by 25% and active-idle power by 300% (clocking arch).
● Reduced overall sequential count by 25% and increased bandwidth by 2x while maintaining the same overall latency.
Collaborated across logic design/verification, analog/physical design, post-silicon validation, manufacturing, firmware, and SoC+MC architecture/design teams.
● Led architectural specifications and design implementations across 100+ features
o Clock network and gating micro-arch with CDC/MCP spec, FIFO/DLL+PI/Deskew
o Per-channel DFI and PM, PHY DFVS/retention states, Reset/Init/Training flows
o Training hardware vs. firmware interface definition and latency optimization
o Timing/STA, TAP/IEEE1500, ATPG/Fault-grading, BIST Loopback, Security review
● Drove quality, efficiency, and inclusiveness by focusing on continuous reviews of arch documentation, logic features/code, verification/bugs, and physical design.
Architected industry-leading feature set – state-of-the-art IO link training solution – including Tensilica µ-controller, drop-in firmware package, and highly programmable sequence and pattern generators.
● Pioneered memory controller independent solution and received a patent.
● Targeted for reuse and generalization across other memory technologies.
● Reduced flop count by 75% over the Intel gold standard with a focused design.
● Improved manufacturing data collection (supports volume testers and lab setups)
A key member of an architecture workgroup that analyzes and drives JEDEC ballots for industry standardization of next-gen memory interface feature set.
