# Lohit Yerva > Logic Design Technical lead at NVIDIA Location: San Francisco Bay Area, United States Profile: https://flows.cv/lohit Technical leader and mentor with 8+ years of experience in logic design and micro-architecture. Excellent written and verbal communication skills used to drive architectural clarity and execution focus. Recognized, by multiple managers and leads, for generating creative and elegant solutions. Passionate about embedded systems and computer architecture. Currently reading through the entire 5th edition of Computer Architecture: A Quantitative Approach by Hennessy & Patterson to refresh my knowledge and appreciation. Focusing on vector and parallel architectures in the newer version of this book, like ARM SVE, Intel AVX, or RISC-V vector extensions. As a personal hobby, I am trying to correlate crazy attic temperatures with living space temperatures (4x Raspberry Pi/ESP32, MQTT, Python/Node-RED, Influx DB, Grafana). ## Work Experience ### Logic Design Technical lead @ NVIDIA Jan 2020 – Present | Santa Clara County, California, United States ### Logic design Technical lead and Micro-architect @ Intel Corporation Jan 2016 – Jan 2020 | San Francisco Bay Area Led team of 8, mentored 25+ diverse engineers, and delivered a complex mixed-signal memory PHY design (8+ mm^2, 200K sequentials) to multiple SoC customers. ● Delivered new IP, with zero functional bugs, directly to first product silicon. ● Achieved IP bring-up in 12 hours using a brand new link training solution. ● Reduced peak power by 25% and active-idle power by 300% (clocking arch). ● Reduced overall sequential count by 25% and increased bandwidth by 2x while maintaining the same overall latency. Collaborated across logic design/verification, analog/physical design, post-silicon validation, manufacturing, firmware, and SoC+MC architecture/design teams. ● Led architectural specifications and design implementations across 100+ features o Clock network and gating micro-arch with CDC/MCP spec, FIFO/DLL+PI/Deskew o Per-channel DFI and PM, PHY DFVS/retention states, Reset/Init/Training flows o Training hardware vs. firmware interface definition and latency optimization o Timing/STA, TAP/IEEE1500, ATPG/Fault-grading, BIST Loopback, Security review ● Drove quality, efficiency, and inclusiveness by focusing on continuous reviews of arch documentation, logic features/code, verification/bugs, and physical design. Architected industry-leading feature set – state-of-the-art IO link training solution – including Tensilica µ-controller, drop-in firmware package, and highly programmable sequence and pattern generators. ● Pioneered memory controller independent solution and received a patent. ● Targeted for reuse and generalization across other memory technologies. ● Reduced flop count by 75% over the Intel gold standard with a focused design. ● Improved manufacturing data collection (supports volume testers and lab setups) A key member of an architecture workgroup that analyzes and drives JEDEC ballots for industry standardization of next-gen memory interface feature set. ### Senior Hardware Design Engineer @ Intel Corporation Jan 2012 – Jan 2016 | Portland, Oregon Area ● Drove cross-validation of co-simulation models from two external memory vendors and emulation model and filed most bugs/enhancements (68+). ● Used SystemVerilog/OVM/UVM constructs (with OOP and general data structures) to perform transaction modeling and monitoring. ● Exposed silicon fatal clock domain crossing bug two weeks before tape-in, through systematic audit of timing reports on 100K+ paths, in my first year. ### Software Engineering Intern @ Apple Inc. Jan 2010 – Jan 2010 ### Engineering Intern @ Intrepid Control Systems Jan 2008 – Jan 2009 Product research, design and development: NeoMote. Created a new product in 4 months by adding a user facing LED scrolling display to existing hardware and firmware stack, and packaged it with custom enclosure/PCB Developed interrupt driven I2C, SPI, and UART firmware for Bluetooth transceivers ## Education ### Master of Science (MS) in Computer Science University of Michigan - Rackham Graduate School Jan 2011 – Jan 2012 ### BSE in Computer Engineering University of Michigan Jan 2007 – Jan 2011 ## Contact & Social - LinkedIn: https://linkedin.com/in/lohit-yerva-97227019 --- Source: https://flows.cv/lohit JSON Resume: https://flows.cv/lohit/resume.json Last updated: 2026-03-30