A technology-driven professional with 6+ years of experience in ASIC Verification. Experience working in HVL based test environments, developing, implementing test plans, and extracting verification metrics.

2023 — 2025MicrosoftLead Design Verification Engineer, Consultant

2023 — 2025

San Francisco Bay Area

Client : Microsoft.

2020 — 2023MetaSenior Verification Engineer, Consultant

2020 — 2023

California, United States

Client : Meta and Intel

2019 — 2020Achronix Semiconductor CorporationSenior Verification Engineer

2019 — 2020

Santa Clara

2018 — 2019Intel CorporationDesign Verification Engineer, consultant

2018 — 2019

Santa clara

2012 — 2014SmartPlay TechnologiesASIC Verification Engineer

2012 — 2014

Processor Instructions Verification - Chimera

Client: Synaptics

Developed constraints for randomization of instructions.

Responsible for Coverage Analysis(Functional & Code) and Debugging.

One-Wire IP Verification

Client: Texas Instruments

Developed components interface, driver, scoreboard, sequencer and sequence.

Responsible for implementing test cases and verification.

Simple SPI IP Verification

Implemented APB interface which communicates with SPI.

Developed components interface, driver, scoreboard, sequencer and sequence.

Implemented APB & SPI Bus Monitors.

Education

Visvesvaraya Technological University

Bachelor's Degree

Visvesvaraya Technological University

Experience+

Education

Bachelor's Degree

Master's Degree