# Manasa Hanakere Krishnappa

> ASIC Verification Engineer | Open to New Opportunities | UVM, SystemVerilog, PCIe, AXI, SVA

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/manasahanakerekrishnappa

A technology-driven professional with  6+ years of experience in ASIC Verification. 

Experience working in HVL based test environments, developing, implementing test plans, and extracting verification metrics. 

An energetic, self-motivated individual with hands on experience in Programming, Requirements Gathering, Assertions and Coverage Analysis(functional and code). 


Technical Skills:

Hardware Languages(HDL/HVL): Verilog, System Verilog 
Programming Languages: Familiar with Perl, C, C++
Verification Methodologies: OVM, UVM
Arm Bus Protocols(AMBA): AHB, APB, AXI
Other Bus Protocols:  SPI
Tools: Cadence, Quartus, VCS, Xilinx, Altera Maxplus2
Assembly Languages: 8085, 8086, 8051
Programmable Logic Devices: FPGA, CPLD

## Work Experience
### Lead Design Verification Engineer, Consultant @ Microsoft
Jan 2023 – Jan 2025 | San Francisco Bay Area
Client : Microsoft.

### Senior Verification Engineer, Consultant @ Meta
Jan 2020 – Jan 2023 | California, United States
Client : Meta and Intel

### Senior  Verification Engineer @ Achronix Semiconductor Corporation
Jan 2019 – Jan 2020 | Santa Clara

### Design Verification Engineer, consultant @ Intel Corporation
Jan 2018 – Jan 2019 | Santa clara

### ASIC Verification Engineer @ SmartPlay Technologies
Jan 2012 – Jan 2014
Processor Instructions Verification - Chimera                             				    
Client: Synaptics
    - Developed constraints for randomization of instructions. 
    - Responsible for Coverage Analysis(Functional & Code) and Debugging.

One-Wire IP Verification								         
Client: Texas Instruments
    - Developed components interface, driver, scoreboard, sequencer and sequence.  
    - Responsible for implementing test cases and verification.

Simple SPI IP Verification									         
    - Implemented APB interface which communicates with SPI.
    - Developed components interface, driver, scoreboard, sequencer and sequence.
    - Implemented APB & SPI Bus Monitors.

### Project Trainee @ Bharat Electronics
Jan 2010 – Jan 2011 | Bengaluru Area, India
Programmable DSP ASIC Prototype for SONAR
    - Responsible for schematic design.
    - Completed implementation in FPGA


## Education
### Bachelor's Degree in Electronics & Communication Engineering
Visvesvaraya Technological University

### Master's Degree in VLSI Design and Embedded Systems
Visvesvaraya Technological University


## Contact & Social
- LinkedIn: https://linkedin.com/in/manasa-hanakere-krishnappa

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Source: https://flows.cv/manasahanakerekrishnappa
JSON Resume: https://flows.cv/manasahanakerekrishnappa/resume.json
Last updated: 2026-03-30