• Seasoned digital architect/manager with over thirty years of hands-on experience in various phases of ASIC design, including architecture, implementation (fluent in Verilog/VHDL RTL coding), functional verification, synthesis, ECO, formal verification, static timing & power analysis, and silicon debug; also exposed...
Experience
2018 — Now
2007 — 2018
1995 — 1997
1994 — 1995
Education
Birla Institute of Technology and Science, Pilani