# Manikantan Jayaraman

> Digital Design Manager at Texas Instruments

Location: San Jose, California, United States
Profile: https://flows.cv/manikantan

•	Seasoned digital architect/manager with over thirty years of hands-on experience in various phases of ASIC design, including architecture, implementation (fluent in Verilog/VHDL RTL coding), functional verification, synthesis, ECO, formal verification, static timing & power analysis, and silicon debug; also exposed to backend related activities
•	Experienced in leading and managing various ASIC projects, particularly mentoring junior engineers
•	Consistently produced many “first-time-right” ASICs
•	Demonstrated fluency in written/oral communication through architecture documentations and their presentations.
•	Established an enriched inter-personal skill by interfacing with offshore (non-native English speaking) engineers
•	Detail-oriented with a committed attitude
•	Exposed to a wide area of applications such as SerDes, Ethernet MAC, Ethernet Switch, mobile IoT, Transport Demux of Set-top box, Set-top box Security, Cable modem (DOCSIS MAC 802.14), Wireless modem (CDMA-IS95), ARM-based peripherals, and signal processing (implementing DSP elements); specialized in designing MAC layer for networking ASICs
•	Tools Used:  Verilog & VHDL simulators (NCSIM, Modelsim), Synopsys: DC compiler (synthesis), Prime Time (Static timing), Magma: Talus Design, Codescape (Silicon debug), C-Shell/bash/Perl/tcl/C/UVM/Assembly programming for RTL verification
•	Have filed three patents all of which have been approved.

## Work Experience
### Digital Design Manager @ Texas Instruments
Jan 2018 – Present | United States

### ASIC Design Manager @ Sigma Designs Inc.
Jan 2007 – Jan 2018 | United States

### Sr.Staff Design Engineer @ Philips Semiconductors / NXP
Jan 1997 – Jan 2007

### Sr. Hardware Engineer @ HCL-HP
Jan 1995 – Jan 1997

### Design Engineer @ Compsoft Ltd
Jan 1994 – Jan 1995 | Chennai, Tamil Nadu, India

### Member of Technical Staff @ Intersoft Technologies
Jan 1994 – Jan 1994 | Noida, Uttar Pradesh, India


## Education
### M.E. in Microelectronics
Birla Institute of Technology and Science, Pilani


## Contact & Social
- LinkedIn: https://linkedin.com/in/manikantan-jayaraman-749b40

---
Source: https://flows.cv/manikantan
JSON Resume: https://flows.cv/manikantan/resume.json
Last updated: 2026-04-13