o Lead a team of software developers to develop FGPA timing model based STA engine to support in-house FPGA prototyping tool.

o Enhanced FPGA Timing Model based STA for system level timing analysis to ensure sub-liear run time increase in STA timing propagation due to design size increase.

o Enhanced FPGA Timing Model to support distributed TDM scheduling.

o Enhanced FPGA Timing Model to support global router.

o Worked on SLR delay compensation & budgeting to achieve better board QOR.

o Fixed STA issues with TDM.

Worked as a developer for PrimeTime.

○ Lead engineer for UPF (Unified Power Format) module of the engine.

○ Worked as lead engineer to create the new PG verilog flow for PT. This flow

automatically generates rail connectivity from PG verilog.

○ Enhanced different PT flow including hierarchical timing, ETM, ECO to adapt

the new PG verilog flow.

○ Architected UPF writer for bottom-up hierarchical timing flow.

○ Created the infrastructure to read, store, apply and report UPF constraints in

timing graph.

○ Successfully redesigned search algorithm to get 5X runtime improvement for

runtime.

○ Enhanced code to read and store library data in fixed units instead of library

units. Modified code in different part of timing engine including delay

calculation and all client modules to use fixed unit instead of library units.

○ Fixed customer issues, memory corruptions/leaks.

Worked as a developer for Static Timing Analyzer (STA) engine for FPGA synthesis

tool.

○ Fixed issues in timing update, reporting, constraint reading.

○ Fixed issues in forward annotation.

○ Fixed issues in constraint checker.

○ Enhanced code to read in Xilinx timing models instead of in-house models.

○ Implemented model checker. This involves creating a database of the timing

models and running various sanity checking on the model.

○ Fixed bugs to resolve customer cases.

Dec,2001-Feb,2008, Member of Technical Staff ,