# Manzurul Khan

> Software Architect at Cadence Design Systems

Location: San Jose, California, United States
Profile: https://flows.cv/manzurul

## Work Experience
### Software Architect @ Cadence Design Systems
Jan 2024 – Present

### Sr Principal Software Engineer @ Cadence Design Systems
Jan 2021 – Present | San Jose
o Lead a team of software developers to develop FGPA timing model based STA engine to support in-house  FPGA prototyping tool.
o Enhanced FPGA Timing Model based STA  for system level timing analysis to ensure sub-liear run time increase in STA timing propagation due to design size increase.
o Enhanced FPGA  Timing Model to support distributed TDM scheduling.
o Enhanced FPGA Timing Model to support global router.
o Worked on SLR delay compensation & budgeting to achieve better board QOR.
o Fixed STA issues with TDM.

### Principal Software Engineer at @ Cadence Design Systems
Jan 2018 – Present | San Jose, California, United States

### R&D Engineer @ Synopsys
Jan 2008 – Jan 2018
Worked as a developer for PrimeTime.
○ Lead engineer for UPF (Unified Power Format) module of the engine.
○ Worked as lead engineer to create the new PG verilog flow for PT. This flow
automatically generates rail connectivity from PG verilog.
○ Enhanced different PT flow including hierarchical timing, ETM, ECO to adapt
the new PG verilog flow.
○ Architected UPF writer for bottom-up hierarchical timing flow.
○ Created the infrastructure to read, store, apply and report UPF constraints in
timing graph.
○ Successfully redesigned search algorithm to get 5X runtime improvement for
runtime.
○ Enhanced code to read and store library data in fixed units instead of library
units. Modified code in different part of timing engine including delay
calculation and all client modules to use fixed unit instead of library units.
○ Fixed customer issues, memory corruptions/leaks.

### Sr. software engineer @ Synplicity INC
Jan 2008 – Jan 2008
Worked as a developer for Static Timing Analyzer (STA) engine for FPGA synthesis
tool.
○ Fixed issues in timing update, reporting, constraint reading.
○ Fixed issues in forward annotation.
○ Fixed issues in constraint checker.
○ Enhanced code to read in Xilinx timing models instead of in-house models.
○ Implemented model checker. This involves creating a database of the timing
models and running various sanity checking on the model.
○ Fixed bugs to resolve customer cases.
Dec,2001-Feb,2008, Member of Technical Staff ,

### Member of Technical Staff @ Sun Microsystems
Jan 2001 – Jan 2008
Worked as a developer for Static Timing Analysis(STA) tool to support the need of
the 16 core microprocessor design.Designed and implemented different algorithms
in order to add features. Fixed bugs, memory leaks, segmentation faults etc.,
architected and refactored code to optimize memory, runtime and robustness.
○ Designed and Implemented Donut Model for hierarchical timing. This involves
creating models of the sub graphs that can be used in higher level timing
graph for faster run.
○ Implemented Reverse Donut Model for hierarchical timing. This involves
creating model of graph superset that can be used in lower level run. Own a
patent for this.
○ Refactored path reporting and path tracing for robustness. This involves
finding shortest paths and subpaths in timing graph.
○ Implemented reporting on internal register to register paths by constraint
management.

### Design Engineer @ ST MICROELECTRONICS
Jan 2000 – Jan 2001
Debugged X86 design netlist in emulation environment using Quickturn.
○ Modified BIOS and DOC code to bypass bugs.
○ Reproduced the bug in RTL simulation environment.
○ Detected bug in RTL which caused Keyboard malfunction.
○ Detected bug in RTL which caused incorrect command execution.
● Debugged design by running embedded BIOS and DOS code.


## Education
### Master's degree in Electrical and Electronics Engineering
Colorado State University


## Contact & Social
- LinkedIn: https://linkedin.com/in/manzurul-khan-65b4167

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Source: https://flows.cv/manzurul
JSON Resume: https://flows.cv/manzurul/resume.json
Last updated: 2026-04-12