# Mauli Shah

> Product Engineer(Calibre Interfaces) at SIEMENS 

ex-Cadence product engineer (Innovus)

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/maulishah

Looking for new opportunities in USA - more preference to Bay Area 

~ 7 years of industry experience (USA) in backend VLSI/ physical design along with Masters from Arizona State University 

Already having USA work authorization 

▪working as a product engineer(full time) in EDA industry (physical design and verification) since Jan 2020 in Bay Area   

▪Summer Intern 2019 at Cadence Design Systems - San Jose

▪Masters in electrical engineering from ASU with GPA:4.0/4.0

▪Engineering Graduate Fellowship award 2019-2020 from Arizona State University
▪Engineering Graduate Fellowship award 2018-2019 from Arizona State University
▪Graduate Teaching Assistant for Analog and Digital Circuits at Arizona State University
▪Graduate Services Assistant for Analog and Digital Circuits at Arizona State University

▪Technical Skills:
  -Physical Design / PnR tool Innovus and fusion compiler 
- Physical Verification - Calibre 
- advanced node technology

## Work Experience
### Product Engineer - Calibre Interfaces (Physical Design and Verification) @ Siemens EDA (Siemens Digital Industries Software)
Jan 2026 – Present | Santa Clara, CA

### Product Engineer - Calibre Interfaces (Physical Design and Verification) @ Siemens EDA (Siemens Digital Industries Software)
Jan 2024 – Jan 2026 | Fremont, CA

### Lead Product Engineer ( innovus - Physical design ) @ Cadence Design Systems
Jan 2023 – Jan 2024 | Bengaluru, Karnataka, India

### Lead Product Engineer ( innovus ) (physical design) @ Cadence Design Systems
Jan 2022 – Jan 2023 | San Jose, California, United States
Innovus

### Product Engineer II (Innovus) (Physical Design) @ Cadence Design Systems
Jan 2020 – Jan 2022 | San Jose
Cadence Innovus team

### Graduate Teaching Assistant @ Arizona State University
Jan 2019 – Jan 2019 | tempe , Arizona
Analog and Digital Circuits

### Graduate Services Assistant @ Arizona State University
Jan 2019 – Jan 2019 | tempe, Arizona
Analog and Digital Circuits

### Product Engineering Intern (Innovus) @ Cadence Design Systems
Jan 2019 – Jan 2019 | San Jose, California
--Detail study about overall flow of Innovus -Floor Planning,Placement,CTS, Routing,Optimization
--Worked closely with Routing team of Cadence Innovus (EDA)
--Worked on DRC problems in Physical Design related to routing
--Detail study of routing design flow in Innovus (Global Routing/Detail Routing)
--Timing / Power Optimization at different stages of Physical Design
--Use of different kinds of Vias for Post-Route Optimization
--Use of different masks for different technology nodes
--Timing optimization for Clock nets and signal nets using NDR rules
--Signal Integrity for clock and signal nets

### Programmer Analyst Trainee @ Cognizant
Jan 2013 – Jan 2013 | Hyderabad Area, India
Programming tasks in C and C++


## Education
### Master's degree in Electrical and Electronics Engineering (VLSI)
Arizona State University
Jan 2018 – Jan 2019

### Bachelor of Technology - BTech in Electrical, Electronics and Communications Engineering
Nirma University
Jan 2009 – Jan 2013

### XII
C.N. Vidhyalaya (Gujarat Secondary and Higher Secondary Education Board-India)
Jan 2009 – Jan 2009

### C.N. Vidhyalaya (Gujarat Secondary and Higher Secondary Education Board-India)
Jan 2007 – Jan 2007


## Contact & Social
- LinkedIn: https://www.linkedin.com/in/mauli-shah-6b449b155

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Source: https://flows.cv/maulishah
JSON Resume: https://flows.cv/maulishah/resume.json
Last updated: 2026-04-07