Led verification for various IPs including memory IO pads, mixed signal designs and PLLs.

Created infrastructural methodologies and used Jenkins allowing for CI/CD of various behavioral models as well as testbenches.

Migrated the backend for the internal tools to PostgreSQL database.

Designed a new web app leveraging the proprietary project based information for the new in-house regression system with capabilities to incorporate test-plans, run test, execute verification, create bugs, notify owners/team and track various coverage metrics in the entire project cycle for a set of IPs. Leveraged APIs for Confluence, NVBugs, and other in-house tools. Tech stack involved: React, Python, PostgreSQL database

Driven the effort for enhancing code development by leveraging AI tools to increase productivity.

Performed unit-level verification for the mixed signal IPs along with circuit designers to deliver speed of light models.

Supported GPU infra team for making sure the tree builds are in good shape delivering a steady environment to the various stakeholders for development and verification work.

Helped in hiring and mentoring new engineers to be an asset with proper knowledge transfer and ramp-up schedules.

Worked with a team member to create a software tool using python to help in computing the branch coverage for the Firmware w.r.t to the simulations ran.

Responsible for the weekly releases of clean simulation environment including generation of RTL/GATE/WREAL Netlists - reducing and flattening them to lessen the simulation time.

Validated the FW and RTL for the new feature in 140/150s projects which strategize the peak currents and power utilization by the whole system. Created behavioral model in System Verilog and wrote assertions to achieve a full functional, fw and rtl coverage.

Helped in optimizing the validation environment by increasing the functionality checks using CSV for the ongoing projects.

Built an environment for UVM based verification of RTL module using a behavioral model.

Wrote constraints and assertions to check functionality and perform coverage analysis.