# Michael Berg > Principal Compiler Engineer at SiFive Location: Brookdale, California, United States Profile: https://flows.cv/michaelberg I am a compiler writer and designer. My work has been focused on SSA, flow and loop optimizer design and implementation, in code generator design and implementation, on profile based optimizations and on highly optimized compiler runtime support on a large number of compilers, tools and targets. Computer Architectures: Intel{x64, x86, Itanium}, Power{3,4}, AlphaAXP{Ev4..6}, CrayX{1..2}, Gen{7..10}, LWP, MTA, ARM and RiscV. Operating Systems: Windows(95, XP, 7..10), Linux(Suse, Ubunto, RedHat, Android), Solaris, OpenVMS, VMS, MacOS and DigitalUnix. Languages: C, C++, Fortran, Java, Ada, VisualBasic, C# and Chapel Frameworks/APIs/Libraries: STL, MFC, Libm, .Net, RTTI, GLib, OpenMP, MPI, OpenCL, OpenGL and Metal ## Work Experience ### Principal Compiler Engineer @ SiFive Jan 2021 – Present | San Mateo, California, United States ### GPU Compiler Engineer @ Apple Jan 2017 – Jan 2021 | Cupertino, CA I was a member of the backend code generation and performance optimization team. My work was focused on enabling current and future devices, analyzing generated code and implementing optimizations to enhance performance. This includes enabling numerics support, creating new math compilation models and designing/implementing math algorithms and features in the LLVM compiler with aspects in Open Source. ### Sr Staff Compiler Engineer @ Intel Corporation Jan 2012 – Jan 2017 | Santa Clara, CA While at Intel I was a member of the JVM compiler team, leading Intel's Graal compiler effort while doing major compiler implementations in the c2 optimizing compiler at the same time. I implemented loop transformations, extended vectorization, added new machine descriptions, code generators, assemblers and related support, scalar reductions, unrolling guidance of vectorizable loops, vector drain loops, loop splitting, range check elimination and unrolling and designed and implemented a pre-register allocation register pressure scheduler; all for current and future Intel architectures and on multiple implementations of the Java optimizing compiler. While working in a prior role, I Developed optimizations in the OpenCL compiler tool chain for Intel-GPU architectures. Authored and implemented Region Prescheduling for GPUs, including efficient register pressure management, inner-most loop and basic block code motion, global code motion and other region based optimizations. Co-authored SSA based treescan register allocation, contributing complex flow functionality of nested and inner most loop support among other areas. Implemented outlining via function calls, loop optimizations, context sensitive liveness, hierarchical flow based inlining and its heuristics as well as OpenCL language features in LLVM and some proprietary compiler back ends. ### SMTS Compiler Engineer @ AMD Jan 2006 – Jan 2012 | Portland, Oregon Area While at AMD I was a member of the Open64 compiler team. I authored optimizations such as control flow based fully unrolling, best fit unrolling guided by register pressure, register pressure optimizations during code generation, authored memory lib routines using multiversioning, implemented profile based indirect inlining, conditional region merging, context sensitive interprocedural optimizations, loop distribution and peeling, a post register allocation dispatch scheduler, peephole optimizations, multiversioning for interior pointers/alignment (patented) and I wrote the Bulldozer machine model while being the lead engineer over code generator development. I also re-targeted Linux compilers to native Win32 which included a full range of tools and runtime support. The emphasis of this role was mitigating performance on AMD architectures for Spec benchmarks. Finally, I was the lead engineer of the Family 15h Software Optimization Guides for over 3 years. Also, I collaborated in hand optimizing prototype optimizations in many SPEC CPU2006 INT and FP metrics. ### Compiler Engineer IV @ Cray Inc. Jan 2004 – Jan 2006 | Seattle, WA While working in the Programming Environments group targeting the DARPA funded Cascade Architecture, I re-targeted our back end compiler and optimized global hierarchical graph coloring register allocators, local register allocators, implemented various machine descriptions and code generators for a MTA-like parallel processor, for the Opteron, and for the Black Widow processor and authored pre/post local schedulers in the compiler back end for the C/C++/F95 compilers. I also wrote an Opteron encoder for specific target work, as well as designed and implemented the code generation schema for blending a two processor co-code generation of simultaneous target emit to facilitate code generation of parallel workloads on two different architectures as part of the Cascade architecture. ### Staff Compiler Engineer @ Intel Corporation Jan 1999 – Jan 2004 | Bellevue, WA While working for the Managed Runtime Engineering group, I was the lead engineer for JIT compiler development, implementing pre/post register allocation instruction schedulers (global/local), encoders, designing improvements to register allocation and code generation optimizations as well as arraycopy optimizations, redundant load elimination and a large page implementation for a partner JDK. I co-authored a white paper for Pointer Cache and PTLB Implementation for Intel Architectures. Designed and implemented IDRC, an internal Itanium based Java compiler back end which included encoders and decoders, final schedulers, register allocation and an Intermediate Representation of my own making. Before that I worked in the Software Solutions Group, where I designed a post link optimizer for Itanium, implemented call graph and layout optimizations as well as peephole optimizations. The tool was used to optimize static workloads for performance on that architecture. Also I wrote many key functions in customer applications in Itanium and x86 assembler to optimize performance. ### Systems Engineer IV - Compiler Lead Engineer @ Digital Equipment Corp Jan 1996 – Jan 1999 | Bellevue, WA While in this role, I was the lead engineer for CLAXP, designing implementing front ends, middle ends, back ends and link time code generation for Alpha/AXP Windows in the Microsoft Visual Studio compiler suite. I implemented exception handlers, modifications to the Alpha calling standard, alias analysis, IR mapping optimizations and various language features for the C, C++ and Visual Basic compilers. I was a member of a team that ported a code generator and back end for the UTC/Alpha compiler back end. Finally I was also responsible for working with the WindowsNT group regarding the first bring up of Win64 on Alpha by providing compiler support for that effort as Alpha/AXP was the first system to support that OS. ### Software Engineer @ BEST Consulting Jan 1994 – Jan 1996 | Kirkland, WA Game source development, programming language design and Oracle/Sybase C++ db application development. I developed game play algorithms for many popular board games, designed, developed and extended components of Sierra-onlines internal game source language. ### Software Engineer II @ Litton PRC Jan 1991 – Jan 1994 | Thousand Oaks, CA While in this role, I developed Fortran/C image processing applications and tools utilizing Sybase database support for CATIS 3.0/IESS 1.0. I designed and implemented a Fortran 77/90 to ANSI C source to source translator to port applications to C using an augmented SLR parser design with some state transition table mapping support to handle some of the hard problems like formatting expressions and other recursive components of that grammar. Because of this effort, a large amount of the legacy code base was translated in this manner. ## Education ### Bachelor of Science (BS) in Computer Science and Applied Mathmatics California State Polytechnic University-Pomona ## Contact & Social - LinkedIn: https://linkedin.com/in/michael-berg-16656635 --- Source: https://flows.cv/michaelberg JSON Resume: https://flows.cv/michaelberg/resume.json Last updated: 2026-04-12