Spanner is Google's scalable, multi-version, globally-distributed, and synchronously-replicated database used by many critical Google services such as Google Ads, Gmail, Youtube, Google Docs and GCP etc.

My charter at Google is to improve Spanner reliability to uphold Spanner's five-nines of availability and improve resource isolation between users in the multi-tenant deployment of Spanner for higher resource efficiency.

• Committer of Apache Impala project, an open source, low latency MPP SQL analytic database.

• Led a team of engineers to overhaul the Impala query engine distributed execution framework, resulting in much higher reliability and 6x throughput under large scale deployment (see blog post). This feature is critical in unblocking large scale deployment of Impala for some customers.

• Incrementally improved the query engine's end-to-end latency via LLVM dynamic code generation for expression evaluation, software pipeling + cache prefetching for better join performance. Single-handedly drove the effort to lower the latency of dynamic code generation (50% reduction in latency for short query) via technique such as lazy loading of LLVM IR.

• Participated in calls with customers on various escalation cases and worked closely with support team to identify the root causes and drove the cases to resolution.

• Mentored new hires to help them get up to speed.

Worked on various areas of the core hypervisor at VMware such as memory management, nested virtualization, virtual time keeping, VM migration, VM checkpointing and VM record/replay.

Some interesting things I have built included a prototype for IO directed page sharing, shadow paging for nested virtualization to speed up certain guest OS such as Hyper-V by 2-4x and removing some bottleneck in the hypervisor to achieve 2~3x speedup in memory intensive workload for wide SMP VMs.

Designed test plans for the Bulldozer processor for architectural features which span multiple stages of the pipeline (e.g. self-modifying code). Also looked into test plans for new features in AMD-V (e.g. clean bits support in VMCB).

Improved the performance of a hypervisor when using hardware assisted virtualization:

• deferred interrupt acknowledgement

• streamlined the processing of frequent events such as hidden page faults.