# Michael Yin

> Cybersecurity/IT // ASIC/FPGA

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/michaelyin

Current interests:  Cybersecurity/Information Technology (IT).  Completed courses in CompTIA A+, Security+, CCNA (network routers and switches), Cybersecurity Certificate (May, 2024), Fortinet ForitGate (firewall) Administrator and Fortinet Wireless Security courses (Dec, 2024), Cloud Security Training (Feb, 2025).

ASIC/SoC/FPGA design and verification.
Several full design ASIC cycles: initial specification, algorithm development, C modeling, microarchitecture and RTL design, synthesis and timing closure, functional verification, static timing analysis, FPGA design for hardware emulation, and tapeout.
FPGA design with Xilinx and Achronix FPGAs.  RTL design, synthesis, timing closure, functional verification, and testing in lab/actual system.
My current email address: micyin@gmail.com.

#cybersecurity #IT #FPGA #ASIC #SoC

## Work Experience
### Player @ National Cyber League (NCL)
Jan 2023 – Present
NCL Fall 2023 Competition

### Engineer @ Stealth Startup
Jan 2022 – Present

### FPGA Engineer (lead) @ Neural Propulsion Systems, Inc.
Jan 2022 – Jan 2022 | California, United States
LiDAR FPGA design and verification and testing in the lab and in the field.  Xilinx RF SoC FPGA design, synthesis, and simulation with Vivado.

### Staff Engineer @ Achronix Semiconductor Corporation
Jan 2016 – Jan 2022 | Santa Clara, California, United States
RTL modeling, verification and synthesis of FPGA fabric components.  Implemented Synopsys memory BIST for on-chip memories in a novel FPGA flow.  FPGA design and verification for 16nm and 7nm FPGAs.

### Principal Engineer @ GEO Semiconductor, Inc.
Jan 2016 – Jan 2016
ASIC design of next generation camera video processor. Contributed in micro-architecture, design and verification.  Designed and verified a serial interface in FPGA.

### Senior FPGA Engineer @ Prysm Inc.
Jan 2013 – Jan 2016
RTL (Verilog) design and simulation of video tile control electronics and DSP filters design, designed a new video data path for prototyping, FPGA design with Xilinx Vivado, FPGA verification and debug with ChipScope/Integrated Logic Analyzer and board bring up.

### Sr. Staff Engineer @ SMI
Jan 2010 – Jan 2013 | Santa Clara, CA
Hands-on design and verification of a multimedia subsystem (video & audio) in a SoC.  Create micro-architecture and detail specifications, create algorithms and C models for algorithm evaluation, RTL design and verification, evaluate/select IPs and integrate the IPs in SoC.  Assist verification and emulation of the multimedia subsystem in SoC environment.


## Education
### B.S. in EECS
University of California, Berkeley

### M.S. in EE
Santa Clara University


## Contact & Social
- LinkedIn: https://linkedin.com/in/michaelyin

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Source: https://flows.cv/michaelyin
JSON Resume: https://flows.cv/michaelyin/resume.json
Last updated: 2026-04-10