● Implementing and maintaining timing-critical Power, Performance, Reset, and RAS features in Bare

Metal C++ FW, for multiple server SoC products

● Serving as a Post-Si Debug Support Lead, interfacing with different teams and stakeholders to root

cause analyze, triage, and resolve issues; and maintain manageable workloads for my team

● Considering side effects and cross-products with concurrent architectural features, requiring

coordination with architects / stakeholders

● Performed FW image size reduction through compile-time optimizations, requiring extensive object

assembly inspection

● Programming controller in C to enable product features and HW workarounds, observing maintainable code practices

● Maintaining signal calibration (link training) algorithms in close collaboration with hardware and

validation engineers

● Debugging and verifying FW changes w/ HW debugger, SW model simulation, Python tools, unit

testing framework, etc.

● Extensively using Git for code change team coordination and using Gerrit for code reviews

Hardware accelerator IP functionality test (software) planning, development, documentation, execution, and debug; Knowing the features and functional flows of individual subsystems as well as how they interact over interconnects; Proper, consistent, and reproducible DUT (Design Under Test) system configuration; Stakeholder communication and support