# Mick Thomas Lim

> Silicon FW, System, & Architecture Engineer | Computer Architecture, Science, & Tech Enthusiast

Location: Mountain View, California, United States
Profile: https://flows.cv/mickthomaslim

Seasoned Computer Engineer with expertise in Silicon Firmware, Post-Si Debug (incl. Leading Debug Support for FW), Computer Architecture, and Algorithm Development & Analysis.

Experienced in C, Bare Metal C++, Navigating Architectural Specifications, Pre-Si / Post-Si Debug (data analysis and tools such as those built on TAP / JTAG interface), Assembly Languages, Python, and Bash & Linux.

Known to promote learning and knowledge sharing in my teams and colleague networks, bring culture and camaraderie, and be constantly tuned into company direction, roadmaps, and initiatives, as well as the industry at large.

Also carries interests in computer graphics, mathematical modeling, digital hardware design (VLSI), and analog circuits.

## Work Experience
### Compiler Engineer @ Bolt Graphics
Jan 2026 – Present | Sunnyvale, California, United States

### CPU Virtual Platforms Engineer @ Qualcomm
Jan 2024 – Jan 2025 | Santa Clara, California, United States

### Silicon Firmware Development Engineer @ Intel Corporation
Jan 2021 – Jan 2024 | Santa Clara, California, United States
● Implementing and maintaining timing-critical Power, Performance, Reset, and RAS features in Bare
Metal C++ FW, for multiple server SoC products
● Serving as a Post-Si Debug Support Lead, interfacing with different teams and stakeholders to root
cause analyze, triage, and resolve issues; and maintain manageable workloads for my team
● Considering side effects and cross-products with concurrent architectural features, requiring
coordination with architects / stakeholders
● Performed FW image size reduction through compile-time optimizations, requiring extensive object
assembly inspection

### Silicon Firmware Development Engineer @ Intel Corporation
Jan 2019 – Jan 2021 | Chandler, Arizona, United States
● Programming controller in C to enable product features and HW workarounds, observing maintainable code practices
● Maintaining signal calibration (link training) algorithms in close collaboration with hardware and
validation engineers
● Debugging and verifying FW changes w/ HW debugger, SW model simulation, Python tools, unit
testing framework, etc.
● Extensively using Git for code change team coordination and using Gerrit for code reviews

### System Validation Engineer @ Intel Corporation
Jan 2017 – Jan 2019 | Chandler, Arizona, United States
Hardware accelerator IP functionality test (software) planning, development, documentation, execution, and debug; Knowing the features and functional flows of individual subsystems as well as how they interact over interconnects; Proper, consistent, and reproducible DUT (Design Under Test) system configuration; Stakeholder communication and support

### Technical Marketing Engineer @ Intel Corporation
Jan 2017 – Jan 2017 | Folsom, California, United States
Comprehending the technical needs of a market (taking into account profit opportunities), catering hardware features to those needs, working with the relevant owners & subject matter experts to achieve goals, documenting & stitching together system configuration recipes, and creating physical demos

### Computer Science Teaching Assistant @ Arizona State University
Jan 2016 – Jan 2016 | Tempe, Arizona

### Computer Science Tutor @ Glendale Community College
Jan 2013 – Jan 2015 | Glendale, Arizona


## Education
### BSE in Computer Systems Engineering
Arizona State University

### Associate in Science in Engineering Technology
Glendale Community College

### Computer Science
Trinity University of Asia

### Elementary in Not Applicable
Saint Joseph's College of Quezon City


## Contact & Social
- LinkedIn: https://linkedin.com/in/mick-thomas-lim

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Source: https://flows.cv/mickthomaslim
JSON Resume: https://flows.cv/mickthomaslim/resume.json
Last updated: 2026-04-10