# Nadav Hayun

> Innovating Silicon Lifecycle Management

Location: San Jose, California, United States
Profile: https://flows.cv/nadavhayun

## Work Experience
### Sr. Product Manager @ Siemens EDA (Siemens Digital Industries Software)
Jan 2024 – Present | Fremont, California, United States

### Co-Founder & CPO @ JOBIT - Commercial Real Estate Maintenances Automation
Jan 2023 – Jan 2024 | San Jose, California, United States
Product Manager for an AI-powered commercial property maintenance platform, deeply engaged with customers to solve real-world pain points. Led cross-functional teams to automate job generation, embed compliance, and streamline vendor bidding—cutting maintenance costs by up to 45%. Owned product messaging and positioning amid a crowded SaaS market, created marketing materials, and presented at industry conferences to drive adoption and growth.

### Co-Founder & CPO @ BuildWiz
Jan 2022 – Jan 2023 | San Francisco Bay Area
Product Manager leading end-to-end delivery of a game-changing home improvement platform. Defined and validated user needs through research, shaping an intuitive experience that helps homeowners clarify project requirements and enables service providers to bid remotely, removing the need for site visits.

Leveraged AI to automate core workflows, including scope creation, contract generation, invoicing, progress payments, and vendor background checks. Spearheaded seamless integration with dozens of third-party services to extend platform capabilities and improve reliability.

Conceived and launched an innovative project escrow solution, enhancing trust and compliance for both clients and vendors while navigating complex legal and geographic challenges. Drove the platform to 1,300 active users and $3M ARR by releasing beta features, overseeing continuous improvement, and removing bottlenecks to accelerate growth.

### Product Manager - Data Center HPC @ Intel Corporation
Jan 2018 – Jan 2022 | Santa Clara
Product Manager driving HPC resource optimization and service improvements for 60,000+ engineers at Intel. Launched and scaled a self-service platform that cut resource provisioning time from days to 90 seconds. Leveraged data analytics and machine learning to reduce storage costs by 25% and cut SaaS spend by 20%. Led cross-functional collaboration and customer beta programs to deliver impactful, scalable solutions with measurable business outcomes.

### Director - Debug Domain, Intel Server Chassis @ Intel Corporation
Jan 2016 – Jan 2018 | Santa Clara
Led strategy and delivery of debug capabilities for Intel’s Xeon servers, driving a 70% reduction in SoC-level bugs and 40% fewer support requests through automated integration and standardized debug interfaces. Partnered cross-functionally to prioritize features, manage risks, and launch scalable, corporate-standard solutions that improve efficiency and customer satisfaction across global teams. Owned roadmap and communications for debug features, ensuring transparency on erratas, bugs, and vulnerabilities.

### Server Power Management Validation Manager @ Intel Corporation
Jan 2016 – Jan 2017 | Santa Clara

### Test Chip Lead and Architect @ Intel Corporation
Jan 2015 – Jan 2016 | San Francisco Bay Area
- Orchestrated the development of automation allowing seamless integration Digital blocks, Analog and mixed signal IPs which were dropped at the last minute into a Test Chip.
- Partnered with HVM and system validation owners to make Test Chip validation aligned with their methodology and allowing leverage into the final product, and from one Test Chip to another. Test chip program was made an asset for silicon validation partners, rather than a burden, cutting their cost significantly and reducing final product's TTM by 2 quarter for the least benefiting IP.
- Envisioned and executed a unified test chip package program to allow re-use of validation hardware and collaterals across test chips and products. Mitigated product risks and drove feedback loop to improve overall TTM by 2 quarters.

### Debug and DFT Architect- WCS @ Intel Corporation
Jan 2014 – Jan 2015 | Petah Tikva Area, Israel
- Architected the WIFI IP buttress to allow integration into multiple SOCs while maintaining compatibility for discrete chip, increasing attach rate by 300% within 3 years.

### Logic Design Manager and Architect- Design for Debug @ Intel Corporation
Jan 2013 – Jan 2014
Client CPU Debug architect and logic design owner

### DFT and Component Debug Manager @ Intel Corporation
Jan 2009 – Jan 2013
- Led cross site silicon debug for 2 SOCs; Justified equipment investment, drove timely install of $3M test and probe machines, and led team through >100 yield issues and circuit sensitivities; Drove smooth cross-functional collaboration, enabling successful PRQs of 2 major > $100M projects (CedarView & CloverView )
- Developed post silicon debug methods for special circuits that became the organization standard and expedited by 2x the process of achieving the product bin-split target comparing to previous generation.
- Led cross site silicon debug for 2 SOCs; Justified equipment investment, drove timely install of $3M test and probe machines,
and led team through >100 yield issues and circuit sensitivities; Drove smooth cross-functional collaboration, enabling
successful PRQs of 2 major > $100M projects (CedarView & CloverView )
- Architected an effective and creative custom on die test and repair solution for external DRAM that path-cleared the usage of
WIO DRAM and enabled the respective memory technology for Atom SOC, resulting in 2x BW at 25% of the power.
- Led the test strategy and HVM configuration for complex SOC, saving 70% of test cost while meeting the DPM target.

### Technical Lead- Component Debug @ Intel Corporation
Jan 2003 – Jan 2009 | Haifa
- Technical lead in Component Debug-  handled debug of yield issues and circuit sensitivity, definition and development of debug and automation, enablement of HVM flows.  
- Spearheaded the development of a low-cost debug tester for CPU project; Built concept and specs, developed FPGA, defined software layer and mitigated mechanical challenges; Delivered and successfully deployed 40 units used for Sandy Bridge CPU debug, saving over $10M; Received VP level award for driving faster TTM in a cost-effective way.

### Test Engineering Intern @ Freescale Semiconductor
Jan 2000 – Jan 2003


## Contact & Social
- LinkedIn: https://linkedin.com/in/nadavhayun

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Source: https://flows.cv/nadavhayun
JSON Resume: https://flows.cv/nadavhayun/resume.json
Last updated: 2026-04-13