● Brought up and optimized large-scale SoC emulation models on Palladium Z2 for pre-silicon validation.

● Optimized emulation model capacity and runtime performance by reducing shadow logic and improving critical paths

● Debugged complex hardware/software interactions in emulation runtime using Verdi, SimVision, and Trace32.

● Enabled Gate-Level Emulation (GLE) flows to support post-synthesis debug and hardware/software co-verification.

● Improved runtime throughput by reducing emulation clock stalls and optimizing model performance.

● Developed automation scripts in Tcl, Python, and Shell to streamline emulation build flows and regression management

• Taking ownership and quickly drive to resolution product issues reported by field AEs and customers

• Debug customer reported failures, produce test cases to replicate failure and log issues with R&D teams.

• Recommend potential workaround or application level solutions to customers when necessary.

• Test R&D fixes/patches.

• Work with customer and internal groups to spec out enhancement requests.

• Testing new product features for future s/w releases or h/w platform, including participation in internal beta activities.

• Engaging in handling critical customer issues to debug failures via webex or Lync.

• Updating and helping to develop product training materials.

Tools:- Cadence Incisive,Synopsys VCS,Verdi,Mento Graphics Mti. UVM

• Worked in an IP team involved in verification of UVM based internal bus protocol VIP.

• Written and updated coverage models for internal bus protocol as per the verification test plan.

• Developed coverage monitors and analyse coverage for internal bus protocol.

• Modifying constraints, updating agents and developing new sequences as per the test plan.

• Running regressions using Synopsys VCS and Cadence IUS to verify the functionality of bus protocol by performing functional coverage analysis.

• Debugged test failures by running waveform simulators such as Verdi.

• Made internal releases to the chip team by adding new functionality to the transactor and adding functional coverage metrics.

• Fixed bugs in bus transactor with respect to implementation of functional coverage as requested by customers.

@ Qualcomm San Jose,CA (Thru ATR International, Sunnyvale-CA)

Tools:- Cadence Virtuoso, ADE, OVM, Eclipse, NxClient, Simvision.

• Worked in an Audio codec processor analog verification team with primarily involved in block level functional verification of the mixed signal schematic based design.

• Written Verification tests in System Verilog as per the test plan of the audio chip.

• Compiled netlist using cadence virtuoso schematic and running regressions using simulators like irun.

• Debugged tests and model failures using waveform debugging tool like Simvision.

• Written sequences in OVM for transmitter, Receiver and clock section for the analog chip top of the audio chip.

• Delivered results to the team for time driven projects to meet the tapeout deadlines.

Tools:- Questasim (Mentor Graphics), Ncverilog (Cadence), Linux

• Worked in PCIe Gen 3.0 PHY layer verification team with primarily involved in verification of LTSSM for PCIe VIP.

• Involved in development of the verification environment consisting of Monitor, Driver, Sequencer and Checker using System Verilog/UVM based testbench.

• Modified and updated the constraints in PCIe PHY layer packet as per the verification test plan.

• Written and updated tests and test cases as per the verification test plan to meet the functional coverage metrics.

• Running regressions for LTSSM sub-states to verify the protocol compliance using simulators like Questasim.

• Written and debugged PCIe test failures as per test plan and created error scenario for additional Test case Development