# Naynesh Shah > Principal Engineer at Ampere Location: San Francisco Bay Area, United States Profile: https://flows.cv/naynesh Principal Emulation Engineer with 11+ years of experience in pre-silicon emulation and simulation acceleration for large-scale SoC designs. Expertise in bringing up complex designs on Cadence Palladium platforms, optimizing emulation capacity and performance, and debugging hardware/software interactions. Proven ability to deliver scalable emulation environments that accelerate verification closure ## Work Experience ### Principal Engineer @ Ampere Jan 2021 – Present | San Francisco Bay Area ● Brought up and optimized large-scale SoC emulation models on Palladium Z2 for pre-silicon validation. ● Optimized emulation model capacity and runtime performance by reducing shadow logic and improving critical paths ● Debugged complex hardware/software interactions in emulation runtime using Verdi, SimVision, and Trace32. ● Enabled Gate-Level Emulation (GLE) flows to support post-synthesis debug and hardware/software co-verification. ● Improved runtime throughput by reducing emulation clock stalls and optimizing model performance. ● Developed automation scripts in Tcl, Python, and Shell to streamline emulation build flows and regression management ### Principal Engineer @ Cadence Design Systems Jan 2020 – Jan 2021 | San Jose, California, United States ### Lead Engineer @ Cadence Design Systems Jan 2014 – Jan 2020 | San Jose, CA • Taking ownership and quickly drive to resolution product issues reported by field AEs and customers • Debug customer reported failures, produce test cases to replicate failure and log issues with R&D teams. • Recommend potential workaround or application level solutions to customers when necessary. • Test R&D fixes/patches. • Work with customer and internal groups to spec out enhancement requests. • Testing new product features for future s/w releases or h/w platform, including participation in internal beta activities. • Engaging in handling critical customer issues to debug failures via webex or Lync. • Updating and helping to develop product training materials. ### Verification Engineer (Consultant with Eteam Inc.) @ Qualcomm Jan 2013 – Jan 2014 | Raleigh-Durham, North Carolina Area Tools:- Cadence Incisive,Synopsys VCS,Verdi,Mento Graphics Mti. UVM • Worked in an IP team involved in verification of UVM based internal bus protocol VIP. • Written and updated coverage models for internal bus protocol as per the verification test plan. • Developed coverage monitors and analyse coverage for internal bus protocol. • Modifying constraints, updating agents and developing new sequences as per the test plan. • Running regressions using Synopsys VCS and Cadence IUS to verify the functionality of bus protocol by performing functional coverage analysis. • Debugged test failures by running waveform simulators such as Verdi. • Made internal releases to the chip team by adding new functionality to the transactor and adding functional coverage metrics. • Fixed bugs in bus transactor with respect to implementation of functional coverage as requested by customers. @ Qualcomm San Jose,CA (Thru ATR International, Sunnyvale-CA) Tools:- Cadence Virtuoso, ADE, OVM, Eclipse, NxClient, Simvision. • Worked in an Audio codec processor analog verification team with primarily involved in block level functional verification of the mixed signal schematic based design. • Written Verification tests in System Verilog as per the test plan of the audio chip. • Compiled netlist using cadence virtuoso schematic and running regressions using simulators like irun. • Debugged tests and model failures using waveform debugging tool like Simvision. • Written sequences in OVM for transmitter, Receiver and clock section for the analog chip top of the audio chip. • Delivered results to the team for time driven projects to meet the tapeout deadlines. ### ASIC Verification Engineer @ PerfectVIPs Jan 2012 – Jan 2013 | San Jose Tools:- Questasim (Mentor Graphics), Ncverilog (Cadence), Linux • Worked in PCIe Gen 3.0 PHY layer verification team with primarily involved in verification of LTSSM for PCIe VIP. • Involved in development of the verification environment consisting of Monitor, Driver, Sequencer and Checker using System Verilog/UVM based testbench. • Modified and updated the constraints in PCIe PHY layer packet as per the verification test plan. • Written and updated tests and test cases as per the verification test plan to meet the functional coverage metrics. • Running regressions for LTSSM sub-states to verify the protocol compliance using simulators like Questasim. • Written and debugged PCIe test failures as per test plan and created error scenario for additional Test case Development ### Student Assistant @ California State University, Northridge Jan 2010 – Jan 2012 | Northridge,CA •Provided customer support to students,staff and faculty. •Troubleshooting wireless networks and VPN for Windows, MAC and Linux systems. ### Jr.Embedded Engineer @ Mtech Innovations Ltd Jan 2007 – Jan 2009 • Assisted senior embedded engineer in designing various modules of Access control system like Real time Clock, display and LCD • Programmed the Philips microcontroller P89C51 using Flash Magic and tested the functionality of microcontroller through hyper-terminal for various card readers like Mifare, Proximity and Biometric access control system. • Responsible for writing test cases for embedded hardware and execute them manually. • Responsible for installation and commissioning of embedded hardware for the Access control system. • Worked as a Team leader managing group of two people for project called Visitor Management System (VMS). • Provided excellent customer support to the clients in troubleshooting Access control systems. ### Embedded systems design intern @ Nital computers Jan 2006 – Jan 2007 • Designed a prototype using microcontroller CY7C68013A or EZ-USB and studied USB 2.0 as well as I2C features of the microcontroller. • Designed hardware components using schematic tools like ORCAD and wrote firmware in Embedded C to implement the system • Programmed microcontroller using Keil compiler and tested the functionality and debugged using development board. • Developed user interface program using visual basic to demonstrate data in user convenient format at PC end ## Education ### M.S in Electrical Engineering specialised in field of Digital and Computer Engineering California State University, Northridge ### B.E in Elecronics and Telecommunication Savitribai Phule Pune University ### Diploma in Industrial Electronics SVCP ## Contact & Social - LinkedIn: https://linkedin.com/in/naynesh-shah-0952a0a --- Source: https://flows.cv/naynesh JSON Resume: https://flows.cv/naynesh/resume.json Last updated: 2026-04-12