# Ning Zhao

> Engineer in semiconductor industry

Location: Santa Clara, California, United States
Profile: https://flows.cv/ningzhao

## Work Experience
### Product Engineer @ Pure Storage
Jan 2026 – Present | United States

### Principal Product Engineer @ Cadence Design Systems
Jan 2022 – Jan 2026 | United States
• Successfully resolved multiple multi-million production line-down issues. 
• Work in close collaboration with the R&D hardware and software teams on the development, 
introduction, and maintenance of emulation products. 
• Produce and deliver test specifications for system level manufacturing screens to meet the required 
hardware coverage, quality, and product requirements.  
• Perform troubleshooting and failure analysis on production issues encountered at manufacturing sites. 
Use data analysis and categorization of failures to determine improvements and provide feedback to the 
Design and Quality teams. 
• Conducted First Article and 2nd source inspection reviews on system hardware components with the 
goal of product cost reduction. 
• Independently designed, ran, and completed system testing of Palladium Z2 emulation control drawers. 
Including defining test scope, generating test case, writing test software and hands-on testing.  
• Performed board level testing and debugging on printed circuit boards during first article inspections 
and debugged failing cases encountered during production.  
• Developed specific configurations of the GNU/Linux operating system for specialized tasks. 
Implement software to automate the process which included BIOS modification, operating system 
configuration, network setup, software environmental setting, etc.   
• Created python & Bash scripts for systems automation tests to improve test efficiency of emulation 
systems.

### Lead Product Engineer @ Cadence Design Systems
Jan 2018 – Jan 2022 | San Francisco Bay Area
Core Product Engineer for Cadence Palladium emulation platforms
• Testing/debugging FPGA emulation boards of the next generation of Cadence Prototype Platform.
•  DVT, EDVT test for the boards and systems.
• Diagnosed/debugged on the automation test flow for systems which improves manufacturing test efficiency and yield.
• Resolved customer’s technical issues on Emulation Platforms with FSE/AE team.
• Worked with R&D team, test team, production team and contract manufacture to fast deliver products to customer.

### Application Test Engineer @ American Portwell Technology, Inc.
Jan 2015 – Jan 2018 | Fremont
• Board/System level testing/validation, subsystem & circuit testing and validation, troubleshooting and failure analysis.
• Customer issue duplicate and troubleshooting under both Windows and Linux system. Linux OS (CentOS, Ubuntu) package/configuration. Onsite/remote customer support.
• Develop test equipment strategies with the Engineering team to ensure product performance during all phases of product life cycles. Provide real time status update & help to facilitate forecast requirement.
• Work closely with the R&D to find solutions for technical issues and recommend and drive improvements in product capabilities and quality.

### Research Assistant @ University at Buffalo (UB)
Jan 2014 – Jan 2015
This research is based on the comprehensive theory of causality represented by Judea Pearl that offered a methodology which can, in some cases, determine the causal effect between one random variable and another from raw statistical data.
• Developed a new definition as causal strength to quantify causality between two variables (events). Mathematical analysis on quantifying causality.
• Implemented all the simulations in C and matlab, and analytical work based on probabilistic and statistics.

### Teaching Assistant @ University at Buffalo (UB)
Jan 2014 – Jan 2015
I am a teaching assistant for the sophomore/Junior class "Digital Principles"​ in Fall 2014 and graduate class "Information Theory and Coding" in Spring 2015. My responsibility includes the following.
Holding Q/A office hour, demonstrating concepts and solutions and deciding course pace with the professor.

### Design Engineer Intern @ Dalian Institute of Chemical Physics, Chinese Academy of Sciences, China
Jan 2013 – Jan 2013
• 	Implemented the hardware of digital microfluidic system on Altera DE2-115 FPGA with 50MHz clk.
•	Established the communication between the system and computer in Verilog.
•	Developed a standard electronic control laboratory for real-time multi-droplet manipulation.


## Education
### Master’s Degree in Electrical and Electronics Engineering
University at Buffalo
Jan 2013 – Jan 2015

### Master's degree in Marine Transportation
Dalian Maritime University
Jan 2011 – Jan 2013

### Bachelor's degree in Electrical and Electronics Engineering
Dalian Jiaotong University


## Contact & Social
- LinkedIn: https://www.linkedin.com/in/ning-zhao-71965489

---
Source: https://flows.cv/ningzhao
JSON Resume: https://flows.cv/ningzhao/resume.json
Last updated: 2026-04-07