# Paul Shand

> Software Engineer @ Amazon

Location: Palo Alto, California, United States
Profile: https://flows.cv/paulshand

I am a recent Computer Engineering graduate from UC Santa Cruz, specializing in System Programming. My experience spans technical experience in Python, Verilog, and FPGA System Verification, coupled with proven leadership and team management skills. I excel in roles that merge complex technical problem-solving with strategic team leadership.

## Work Experience
### Software Engineer @ Amazon
Jan 2025 – Present | Sunnyvale, California, United States

### Volunteer @ Computer History Museum
Jan 2024 – Present | Mountain View, California, United States
Volunteering on the IBM 1401 restoration team at the Computer History Museum, I help maintain this iconic computer from the 1960s for live demos. My role involves testing and debugging hardware components to keep it operational for educational purposes.

### Contracted Full Stack Engineer @ Skelton Lab at William & Mary
Jan 2024 – Jan 2024
As a Full Stack Engineer at Skelton Lab, I developed a mobile application in Kotlin and a server in Python, enabling communication through a REST API for image processing. This project significantly enhanced beetle data collection by leveraging advanced image processing techniques, reducing the data collection time from minutes to seconds. This optimization allowed for the accurate counting of hundreds of beetles in mere seconds, vastly improving the efficiency and accuracy of the process. My role involved designing and implementing the application and ensuring seamless communication between the client application and server, resulting in a substantial improvement in data processing speed and reliability.

### Building Operation Manager @ University of California, Santa Cruz
Jan 2022 – Jan 2023 | Santa Cruz, California, United States

### Building Operations Attendant @ University of California, Santa Cruz
Jan 2021 – Jan 2022 | Palo Alto, California, United States

### Software Engineer Intern @ Microchip Technology Inc.
Jan 2023 – Jan 2023 | San Jose, California, United States
During my internship at Microchip, I had the opportunity to work in architecture verification, leveraging my expertise in writing Python scripts to facilitate the creation of large intricate FPGA designs. I led three projects focused on large logic design generation and simulation over a three-month period, requiring a strong understanding of FPGA architecture. I developed an automated design generator using Python, capable of producing 30,000 lines of Verilog for complex random RTL designs in seconds. These designs were subsequently simulated using Microchip tools to gather data on breaking points, resource utilization, and congestion, thereby improving design robustness. My role involved simulating these FPGA designs across different FPGAs to analyze behaviors and identify breaking points within the intricate structures, significantly enhancing the efficiency and reliability of the design process.


## Education
### Bachelor's degree in Computer Engineering
University of California, Santa Cruz


## Contact & Social
- LinkedIn: https://linkedin.com/in/paul-alexander-shand

---
Source: https://flows.cv/paulshand
JSON Resume: https://flows.cv/paulshand/resume.json
Last updated: 2026-04-10