# Pavani Jella

> Vice President, Security EDA @ Silicon Assurance | Multiple Credentials

Location: San Francisco Bay Area, United States
Profile: https://flows.cv/pavanijella

Technology and product strategy leader specializing in EDA software platforms, semiconductor verification
technologies, and commercialization of complex engineering infrastructure products. Proven track record of defining
product vision, launching new EDA capabilities, and translating deep semiconductor engineering innovation into
commercially successful platforms.
At Silicon Assurance, led the strategy and commercialization of Analyz-N , the semiconductor industry’s first gate level hardware security verification and trust assurance EDA platform, helping establish Security EDA as an emerging
category in semiconductor design verification. Directed platform strategy, product roadmap, architecture definition,
pricing and licensing models, investor narrative, and go-to-market execution to drive adoption across semiconductor, defense, and critical-infrastructure markets.
Previously at Synopsys, drove the strategy, development, and early commercialization of a new Signal and Power
Integrity (SIPI) EDA product, securing initial customer adoption and shaping product direction alongside PrimeSim
HSPICE and the PrimeSim simulation suite. Led market discovery, roadmap definition, and executive engagement
with leading semiconductor companies developing memory, SerDes, datacenter, and HPC systems.
Earlier roles across GlobalFoundries, Renesas/IDT, Texas Instruments, and Micron Technology established a strong
technical foundation in signal and power integrity modeling, circuit simulation, EDA tool development, and
semiconductor system architecture, enabling a career that bridges deep engineering expertise with product strategy,
ecosystem development, and market commercialization.
Brings 20+ years of experience across semiconductor design, simulation, and EDA software ecosystems, with a
consistent focus on building new technology platforms, shaping product direction, and driving adoption of advanced semiconductor design and verification technologies.

## Work Experience
### Vice President, Security EDA @ Silicon Assurance
Jan 2023 – Present | Pleasanton, CA
Platform strategy, product roadmap, marketing and commercialization of Analyz-N AI
- the semiconductor industry’s first gate-level hardware security verification
and trust assurance EDA software platform, establishing ‘Security EDA’ as an
emerging category in semiconductor design verification.

### Sr Staff Product Manager, Signal and Power Integrity EDA Software Solutions @ Synopsys Inc
Jan 2021 – Jan 2023 | Sunnyvale, CA
Product line management, strategy, marketing and roadmap planning for Synopsys' Signal and Power Integrity EDA software platforms, including Synopsys' PrimeSim, Prime Wave and HSPICE SIPI.

### Deputy Director, Global Marketing, IP and EDA Ecosystem Strategy @ GlobalFoundries
Jan 2019 – Jan 2021 | Santa Clara
Led global marketing initiatives supporting design enablement solutions across
IP, EDA, ecosystem, and design services partners.

### Sr. Sales Enablement & Solutions Marketing Manager - Product Applications, Training & Global SE @ Renesas Electronics
Jan 2018 – Jan 2019 | United States
Led global sales enablement programs supporting MCU, clock/timing, power,
sensor, and wireless power semiconductor portfolios.

### Project Lead, Contractor - Wireless Power Charging System Modeling & Simulation @ IDT - Integrated Device Technology, Inc.
Jan 2017 – Jan 2017
Led SIMPLIS-based system modeling for wireless charging platforms

### Sr Applications Developer – TI's WEBENCH Online Design, Simulation and Analysis Platform Tools @ Texas Instruments
Jan 2008 – Jan 2017 | Santa Clara, CA
Developed power efficiency and circuit BOM calculators, modeling algorithms and simulation infrastructure for
TI’s WEBENCH® online power design and analysis platform

### Lead – IBIS model generation @ Texas Instruments
Jan 2008 – Jan 2012 | Dallas, TX
IBIS Modeling of high speed digital interfaces for TI’s analog product lines

### Sr. Electrical Modeling and Simulation Engineer @ Micron Technology
Jan 2005 – Jan 2008 | Boise, ID
Developed simulation models supporting DDR memory product releases.


## Education
### University of California, Davis - Graduate School of Management
Jan 2018 – Jan 2021

### Courses in Building Business Models & Negotiation
Stanford University
Jan 2016 – Jan 2017

### Master of Science (MS) in Electrical Engineering
Missouri University of Science and Technology
Jan 2002 – Jan 2004

### Bachelor of Engineering (BE) in Electrical, Electronics and Communications Engineering
Osmania University
Jan 1998 – Jan 2002


## Contact & Social
- LinkedIn: https://www.linkedin.com/in/pavanijella
- Website: http://www.designcon.com/2007/conference/8_wa1.html

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Source: https://flows.cv/pavanijella
JSON Resume: https://flows.cv/pavanijella/resume.json
Last updated: 2026-04-07