# Pavan Kangokar > Solving System-Level Software Problems | Embedded Systems – RTOS, C/C++, ARM Architecture, Linux, Microcontrollers Location: Santa Clara, California, United States Profile: https://flows.cv/pavankangokar • 9+ years industry experience in firmware development for Semiconductor and Automotive products. • Expertise in design and development of firmware for SoC and micro-controllers using variety of micro-architecture such as Tensilica, ARM Cortex-M3/M4, Microchip and SiLabs. • Experience co-developing firmware on variety of pre-silicon, x86 and FPGA based emulation platforms. • Extensively worked on AMBA compatible peripheral interfaces such as GPIO, SPI, I2C, APB-AHB Bridge and CAN. • Hands-on debugging experience using JTAG, gdb, RTL-Firmware simulations and hardware bring-up in lab. • Experience in defining BIST, manufacturing tests and DFx for opto-electrical products in High Volume Manufacturing lines. • Experienced developing firmware compliant with ISO 26262, EN 50128 and Misra C coding guidelines for Automotive and locomotive sub-systems. Programming Languages: C, C++, Python, Assembly Software Toolkits: GCC, Gdb PIN, Matlab, Microsoft Visual studio, LDRA, Winidea and Code write. Protocols: I2C, CAN, SPI, AMBA and TCP/IP. Debugging Tools GNU GDB , JTAG, Valgrind , CAN Datalyser and I2C analyzer Micro-controller platforms: Tensilica Diamond 106 core, TMS 470, Freescale 12X, Arduino Galileo, ARM Cortex M3/4(Stellaris Launchpad), ARM Cortex v8 (Raspberry Pi 3),PIC 32 Quality Control Tools: Polyspace Launcher and Viewer RTOS: OSEK, Free RTOS SDLC V-Curve, Agile Lab Equipment’s Agilent Power supply, Agilent power meter, Agilent temperature sensor, Oscilloscopes, Thermo-temperature Oven, Digital spectrum Analyzer, GPIB Interface. Other Interests: CPU architecture, System on Chip Design, Bootloader, Autonomous Driving Vehicle, DFT, JTAG, Low-power system design, Linux Device Drivers, FPGA Programming, RTOS, Software/Hardware Co-design and Performance characterization. ## Work Experience ### Principal Software Engineer @ Broadcom Inc. Jan 2019 – Present | San Jose, California ### Firmware Engineer @ Intel Corporation Jan 2015 – Jan 2019 | Santa Clara, California Firmware development for data centre products ### Firmware Intern @ Intel Corporation Jan 2014 – Jan 2015 | Santa Clara, California Firmware development for data centre products ### Graduate Researcher @ University of Texas at Dallas Jan 2013 – Jan 2015 Investigated the behavior of Motion planning algorithms under faults by implementing the Fault Injector tool in C++ using Intel’s PIN tool, which instruments dynamic faults during the compile time in the Motion planning Algorithm (RRT and RRT*). Proposed application patching techniques (using C ) that allows faults to prevent catastrophic failures and increases the robustness of Motion Planning algorithms. Identified that Motion planning algorithms tend to contain a large degree of inherent error tolerance (e.g. sampling from random distributions and calculating approximate distances). Set of low overhead algorithm-based resilience techniques can be used to allow for the parts of application which are not inherently error tolerant (e.g. kd-tree control flow), to gracefully fail. Presented research at IEEE Texas Workshop on Integrating System Exploration (TexasWISE) 2015 at Austin. ### Senior Engineer(Firmware) @ Faiveley Transport Jan 2013 – Jan 2013 | Bangalore Improved the functionality, code changes in the various modules of Door Control Unit of European Metros using Embedded C for Freescale 12X microcontroller. Analyzed and reviewed several project documents like Software architecture and design specification, System Functional description, test report Test specifications, Software module design specification. Developed the scripts for executing the test cases for different modules. Carried out Internal and customer Release management. Trained and mentored juniors for successful of the project. ### Software Engineer(Embedded) @ KPIT Cummins Infosystems Limited Jan 2010 – Jan 2013 | Bangalore Designed and maintained Roll Stability Control (RSC) Algorithm using Embedded C for brakes Electronic Control Unit of all the Land Rover SUV models. Performed Integration of suppliers Brakes software with RSC, performed simulation testing by debugging the CAN signals using Datalyser and released the bug free software to the Vehicle test Engineer. Proposed a new Calibration review process by developing automation tool. Which increased development efficiency by 600%. Implemented Control models for Power Management Module using MATLAB, Simulink, Stateflow and also auto-coded the same using Target-link for both fixed point and floating point code. Developed Test Cases and performed Model in Loop and Software in Loop testing for Matlab models. ## Education ### Master's degree in Computer Engineering The University of Texas at Dallas ### BE in Electronics & Communication Engineering Bapuji Institute of Engineering and technology ## Contact & Social - LinkedIn: https://linkedin.com/in/pavan-kangokar-661b5123 --- Source: https://flows.cv/pavankangokar JSON Resume: https://flows.cv/pavankangokar/resume.json Last updated: 2026-04-12