# Pedro Vaz Artigas

> Compiler Engineer at d-Matrix

Location: Santa Clara, California, United States
Profile: https://flows.cv/pedrovazartigas

## Work Experience
### Compiler Engineer @ d-Matrix Corporation
Jan 2021 – Present | Cupertino, CA

### Compiler Engineer @ Cadence Design Systems
Jan 2017 – Jan 2021 | San Jose, CA
Worked on AI/ML back-end compiler development targeting DSPs and AI/ML accelerators.

### Compiler Engineer @ Qualcomm
Jan 2014 – Jan 2017 | Santa Clara, CA
Worked on back-end compiler research and development.

### Compiler Engineer @ Apple
Jan 2012 – Jan 2014 | Cupertino, CA
Worked on back-end compiler development.

### Compiler Engineer @ NVIDIA
Jan 2005 – Jan 2012 | Santa Clara, CA
Worked on compiler development. Worked in compilers for several languages including Cg, GLSL and CUDA. Worked on back-end compilers for graphics architectures.

### Co. Op. Student @ IBM TJ Watson Research Center
Jan 1998 – Jan 1999 | Yorktown Heights, NY
Worked on compiler research. Worked on enabling high level transformations and parallelization in the context of the Java language.

### Software Engineer @ Scopus Tecnologia
Jan 1997 – Jan 1998
Worked on infrastructure for rapid development of web applications, specifically developing COM objects to enable use of ASP in internet banking development. Also worked on smart cards and a secure digital money system based on the SET standard.


## Education
### MS in Computer Science
Carnegie Mellon University

### MS in Eletrical Engineering
USP - Universidade de São Paulo

### BS in Eletrical Engineering
USP - Universidade de São Paulo


## Contact & Social
- LinkedIn: https://linkedin.com/in/pedro-vaz-artigas-63997710
- Portfolio: http://www.cs.cmu.edu/~artigas/

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Source: https://flows.cv/pedrovazartigas
JSON Resume: https://flows.cv/pedrovazartigas/resume.json
Last updated: 2026-04-11