Joined as Senior Staff Diagnostics Software Engineer, promoted to Software Architect.

Software architect for common microprocessor frameworks upon the seL4 microkernel. Responsible components: power management, including internal communication and coordination of ARM Cortex-A & Cortex-M domains, wake/sleep sequencing, TC10 Ethernet switch control, PMIC & e-fuse control, redundancy & fault protection.

Software architect for an internal common RTOS platform for microcontrollers based upon FreeRTOS/SafeRTOS. Responsible components: AUTOSAR Network Management (CAN NM, Ethernet UDPNM), ECU Power State Manager, PDU Management and Router, interfaces for CAN/CAN FD, LIN, SPI. Developed requirements, architectural specifications. Contributed to code, tests, management of projects. Currently deployed on a half-dozen microcontrollers on multiple vehicle platforms.

Senior Staff Diagnostics Engineer, NIO in San Jose, CA. 2016-2021.

Developed firmware on NXP i.MX6 for the central CAN Gateway for NIO’s first generation platform. Developed buildroot Linux system and applications such as UDS (ISO 14229) server, UDS client, DoIP gateway, and firmware update manager. Created reusable Python UDS library for simulation test, verification, and service tool deployment.

Architected NIO’s first on-car FOTA (Firmware Over The Air) update process. Led cross-functional firmware design and implementation of FOTA feature for NIO ES8 and ES6 vehicles, allowing firmware updates of all ECUs. Designed and implemented the FOTA manager using C++/Qt5 to securely download, authenticate, and decrypt software packages, and a FOTA sequencer to apply updates.

Responsible for all aspects of firmware on the Main Bike Board (MBB), the electronic control unit at the center of all models of Zero’s electric motorcycles. The MBB is responsible for coordinating battery connections, safety, sequencing, motor controller supervision, and rider UI. My projects span all aspects of electric motorcycle control and production, including bootloaders, firmware, battery management, specialized software tools to assist motorcycle production, circuit design, and much electrical system debugging.

Developed a MIPI DSI (Display Serial Interface) in Verilog, including master and slave configurations, and bolt-on submodules to support DPI-2 and DBI standards. Communicated with customers to develop feature set. Led the design and implementation, established project milestones, tracked team progress, delegated tasks amongst team members, and published a release schedule.

Ran my own consulting practice for system engineering and FPGA design.

Projects included:

• Write a current consumption monitoring and predictive fuel gauge firmware in C for a high-end Li-ion electric motorcycle.

• Developed a full MIPI D-PHY transceiver in Verilog, including master and slave interfaces for data and clock channels. RTL was delivered with a full regression test exercising all modes of the core.

• Developed bus interfaces for a SDRAM IP core. Wrote full regression testbenches and programmable Bus Functional Models (BFM) for each bus type. Bus interfaces included Altera Avalon, AMBA AHB, and AMBA AXI buses. Cores were targeted for simulation, FPGA, and ASIC. Consulted to other engineers for development of interfaces for Xilinx PLB.