# Peter Hutkins > Embedded Software Engineer Location: Scotts Valley, California, United States Profile: https://flows.cv/peterhutkins My areas of technical expertise are in design methodology and tool development for complex hardware and software systems, and high-speed Verilog logic design. Specialties: electric vehicles, embedded system design and FPGAs ## Work Experience ### Staff Software Engineer @ Glydways Jan 2023 – Present ### Principal Software Architect @ NIO Jan 2016 – Jan 2023 | San Jose, CA Joined as Senior Staff Diagnostics Software Engineer, promoted to Software Architect. Software architect for common microprocessor frameworks upon the seL4 microkernel. Responsible components: power management, including internal communication and coordination of ARM Cortex-A & Cortex-M domains, wake/sleep sequencing, TC10 Ethernet switch control, PMIC & e-fuse control, redundancy & fault protection. Software architect for an internal common RTOS platform for microcontrollers based upon FreeRTOS/SafeRTOS. Responsible components: AUTOSAR Network Management (CAN NM, Ethernet UDPNM), ECU Power State Manager, PDU Management and Router, interfaces for CAN/CAN FD, LIN, SPI. Developed requirements, architectural specifications. Contributed to code, tests, management of projects. Currently deployed on a half-dozen microcontrollers on multiple vehicle platforms. Senior Staff Diagnostics Engineer, NIO in San Jose, CA. 2016-2021. Developed firmware on NXP i.MX6 for the central CAN Gateway for NIO’s first generation platform. Developed buildroot Linux system and applications such as UDS (ISO 14229) server, UDS client, DoIP gateway, and firmware update manager. Created reusable Python UDS library for simulation test, verification, and service tool deployment. Architected NIO’s first on-car FOTA (Firmware Over The Air) update process. Led cross-functional firmware design and implementation of FOTA feature for NIO ES8 and ES6 vehicles, allowing firmware updates of all ECUs. Designed and implemented the FOTA manager using C++/Qt5 to securely download, authenticate, and decrypt software packages, and a FOTA sequencer to apply updates. ### Senior Embedded Systems Engineer @ Zero Motorcycles, Inc. Jan 2012 – Jan 2016 | Scotts Valley, CA Responsible for all aspects of firmware on the Main Bike Board (MBB), the electronic control unit at the center of all models of Zero’s electric motorcycles. The MBB is responsible for coordinating battery connections, safety, sequencing, motor controller supervision, and rider UI. My projects span all aspects of electric motorcycle control and production, including bootloaders, firmware, battery management, specialized software tools to assist motorcycle production, circuit design, and much electrical system debugging. ### Senior Design Engineer @ Northwest Logic Jan 2011 – Jan 2012 | Beaverton, OR Developed a MIPI DSI (Display Serial Interface) in Verilog, including master and slave configurations, and bolt-on submodules to support DPI-2 and DBI standards. Communicated with customers to develop feature set. Led the design and implementation, established project milestones, tracked team progress, delegated tasks amongst team members, and published a release schedule. ### sole proprietor @ Hutkins Consulting Jan 2008 – Jan 2011 Ran my own consulting practice for system engineering and FPGA design. Projects included: - Write a current consumption monitoring and predictive fuel gauge firmware in C for a high-end Li-ion electric motorcycle. - Developed a full MIPI D-PHY transceiver in Verilog, including master and slave interfaces for data and clock channels. RTL was delivered with a full regression test exercising all modes of the core. - Developed bus interfaces for a SDRAM IP core. Wrote full regression testbenches and programmable Bus Functional Models (BFM) for each bus type. Bus interfaces included Altera Avalon, AMBA AHB, and AMBA AXI buses. Cores were targeted for simulation, FPGA, and ASIC. Consulted to other engineers for development of interfaces for Xilinx PLB. ### Senior Hardware Engineer @ Altera Jan 1999 – Jan 2007 | Santa Cruz, CA, and Penang, Malaysia Specified and implemented the back-end architecture of SOPC Builder for automated system generation. Defined a new bus system-- the Avalon bus-- and implemented an innovative Object Oriented HDL generator in Perl ("europa"​) to generate Avalon systems. Participated in the design and development of Nios II CPU pipeline, owning the CPU's hardware debugging and real-time tracing unit (on-chip instrumentation, "OCI"​). Specified, designed, and EMC-tested the first Nios Development Board. Various other FPGA-centric embedded system design tools and hardware IP shipped with Altera's Quartus, Nios II, and SOPC Builder tools. Accepted an expatriate assignment in Penang, Malaysia to start a new engineering group in an established low-cost center, reporting to the U.S. home office. Hired 40 engineers over 2 years, mostly new college graduates. Trained new employees for development jobs in Altera's IP and Software Engineering groups. Developed and instructed an intensive 6-week training program for new hires, covering digital design standards, Verilog and VHDL, Altera's Quartus synthesis and place & route tools, ModelSim, Perl, Java, and embedded design methodologies such as DFT, source control management, and other best practices. Classes were conducted on a biannual basis and open to employees from other engineering groups. Led a team to create all of the Nios II Development Kit example designs-- 80 FPGA system designs for 12 development boards, available in both VHDL and Verilog. We developed Java libraries to automate daily FPGA design generation with current tool builds, and full regression testing in simulation and on hardware. ## Education ### BS in Computer Engineering University of California, Santa Cruz ### UC Irvine ## Contact & Social - LinkedIn: https://linkedin.com/in/phutkins - Website: https://docs.google.com/document/d/e/2PACX-1vTVKXB7py1-EbzFKHtNc3Dbm4SV-po8GyBh_sriDGsH2gMAHI49wCH1TeBQh6AJIBEx3B4y2uscXWY8/pub --- Source: https://flows.cv/peterhutkins JSON Resume: https://flows.cv/peterhutkins/resume.json Last updated: 2026-04-01