# PingChen Liu

> Principal Engineer

Location: Fremont, California, United States
Profile: https://flows.cv/pingchenliu

Expert in custom digital / analog circuit design, having strong hand-on experience in SRAM, Flash memory, biasing circuit, LDO, charge pump, A/D converter, switch cap circuit, comparator, DLL, high speed IO buffer - CTLE, DFE, proven track record for delivering many successful products into market - CPU , flash memory, FPGA, CPLD.  Excellent  project management capability and  people management skill.

## Work Experience
### Principal Engineer @ Intel Corporation
Jan 2015 – Present | San Jose
Technical Lead (Technical Director) on Digital & Analog IP design, Chip level integration & PPA Optimization. Embedded SRAM, Register File, Power management, LDO, ADC, PLL, ESD.
Full chip physical integration

### Sr. Design Manager @ Altera
Jan 2006 – Jan 2015

### Sr. MTS Design Engineer @ Altera
Jan 2004 – Jan 2006


## Education
### MSEE in Electronics, Semiconductor
University of  Michigan - Ann Arbor


## Contact & Social
- LinkedIn: https://linkedin.com/in/pingchen-liu-8bba4b

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Source: https://flows.cv/pingchenliu
JSON Resume: https://flows.cv/pingchenliu/resume.json
Last updated: 2026-04-13