Multicore Discrete Event Simulator
o Developed multi-process parallel discrete event simulator using MPI for faster simulation of Verilog designs on multi-core systems.
o Developed a compile-time algorithm to automatically partition hardware designs modeled in Verilog/VHDL languages into multiple partitions. This was a essential first step to enable parallel simulation and the algorithm was decisive in partitioning the real customer designs for load balancing.
o Developed analysis tool to analyze the performance of parallel simulator. This tool was critical in fine-tuning the performance of the parallel simulator and significantly reduced the debug time in the field.
Hardware Discrete Event Simulator:
o Developed the communication architecture of the multi-core hardware simulator.
o Developed C++ architecture models of the hardware simulator.
o Developed compiler support for the new hardware architecture.
o Developed several modules of the host software to manage the simulator.
Verilog compiler and simulator
o Developed new features and optimizations to a constraint solver in Verilog
simulator.
o Worked on the optimization of the Verilog compiler, performance analysis and
improvements of the simulator software.