I am one of the first engineers at Cyral and have contributed to the architecture and development of several key components of the Cyral data security platform. Being an early engineer gives plenty of opportunities in design, implementation, customer engagements, trouble-shootings which is very rewarding. Following are some high level contributions i have made.

* Architected Cyral's high performance and low latency Layer-4 and Layer-7 datapath components for SQL and NoSQL data repositories.

* Designed and developed Cyral's SQL query analyzer algorithm, configuration object model, gRPC/REST APIs

* Designed alerting, logging and metrics framework

* Designed key features such as federation, identity attribution

* Contributed to the development of cloudformation, terraform and kubernetes deployment form factors

Contributed to the debug and profile technologies for Xilinx OpenCL FPGA stack

* Developed debugger for Xilinx OpenCL Runtime. Provided gdb extensions to give visibility into the OpenCL data structures.

* Developed tools to debug the application hangs on FPGA accelerators. Helped with debugging many customer application hangs on FPGA.

* Developed protocol analyzer to analyze the parallelism between the dataflow processes in the HLS generated compute kernels. The analyzer is implemented as an extension in the Xilinx Vivado Simulator.

* Contrubuted to the development of AXIMM and AXIStream protocol analyzer in the Xilinx Vivado Simulator

Multicore Discrete Event Simulator

o Developed multi-process parallel discrete event simulator using MPI for faster simulation of Verilog designs on multi-core systems.

o Developed a compile-time algorithm to automatically partition hardware designs modeled in Verilog/VHDL languages into multiple partitions. This was a essential first step to enable parallel simulation and the algorithm was decisive in partitioning the real customer designs for load balancing.

o Developed analysis tool to analyze the performance of parallel simulator. This tool was critical in fine-tuning the performance of the parallel simulator and significantly reduced the debug time in the field.

Hardware Discrete Event Simulator:

o Developed the communication architecture of the multi-core hardware simulator.

o Developed C++ architecture models of the hardware simulator.

o Developed compiler support for the new hardware architecture.

o Developed several modules of the host software to manage the simulator.

Verilog compiler and simulator

o Developed new features and optimizations to a constraint solver in Verilog

simulator.

o Worked on the optimization of the Verilog compiler, performance analysis and

improvements of the simulator software.

* Implemented code generator to create timed SystemC models from SysML state charts. This work was part of System level modeling and design tool.

* Represented Cadence at Accellera standards organization and contributed to the standardization of Standard Co-Emulation Modeling Interface (SCE-MI 2.1).