# Pramod Chandraiah > Engineer Location: Redwood City, California, United States Profile: https://flows.cv/pramodchandraiah I have over 15 years of experience developing software for computer systems ranging from low level embedded systems to cloud applications. In my past roles I have worked in the areas Compilers, profilers, debuggers, discrete event simulation and constraint random solvers. More recently in the last 4 years, I am working in the area of data security where I am focussed on developing proxying technologies for SQL/NoSQL database protocols and SQL analysis. Most of my development experience is in C/C++, Golang and have developed and deployed software as both monolith as well as microservices. Competencies: Compilers, Database protocols, SQL, Cloud computing, Golang/C++ ## Work Experience ### Software Engineer @ Findem Jan 2022 – Present | Redwood City, California, United States ### Software Engineer @ Cyral Jan 2018 – Jan 2022 | Redwood City I am one of the first engineers at Cyral and have contributed to the architecture and development of several key components of the Cyral data security platform. Being an early engineer gives plenty of opportunities in design, implementation, customer engagements, trouble-shootings which is very rewarding. Following are some high level contributions i have made. * Architected Cyral's high performance and low latency Layer-4 and Layer-7 datapath components for SQL and NoSQL data repositories. * Designed and developed Cyral's SQL query analyzer algorithm, configuration object model, gRPC/REST APIs * Designed alerting, logging and metrics framework * Designed key features such as federation, identity attribution * Contributed to the development of cloudformation, terraform and kubernetes deployment form factors ### Senior Staff Software Engineer @ Xilinx Jan 2016 – Jan 2018 | San Francisco Bay Area Contributed to the debug and profile technologies for Xilinx OpenCL FPGA stack * Developed debugger for Xilinx OpenCL Runtime. Provided gdb extensions to give visibility into the OpenCL data structures. * Developed tools to debug the application hangs on FPGA accelerators. Helped with debugging many customer application hangs on FPGA. * Developed protocol analyzer to analyze the parallelism between the dataflow processes in the HLS generated compute kernels. The analyzer is implemented as an extension in the Xilinx Vivado Simulator. * Contrubuted to the development of AXIMM and AXIStream protocol analyzer in the Xilinx Vivado Simulator ### Staff Software Engineer @ Mentor Graphics Jan 2009 – Jan 2016 Multicore Discrete Event Simulator o Developed multi-process parallel discrete event simulator using MPI for faster simulation of Verilog designs on multi-core systems. o Developed a compile-time algorithm to automatically partition hardware designs modeled in Verilog/VHDL languages into multiple partitions. This was a essential first step to enable parallel simulation and the algorithm was decisive in partitioning the real customer designs for load balancing. o Developed analysis tool to analyze the performance of parallel simulator. This tool was critical in fine-tuning the performance of the parallel simulator and significantly reduced the debug time in the field. Hardware Discrete Event Simulator: o Developed the communication architecture of the multi-core hardware simulator. o Developed C++ architecture models of the hardware simulator. o Developed compiler support for the new hardware architecture. o Developed several modules of the host software to manage the simulator. Verilog compiler and simulator o Developed new features and optimizations to a constraint solver in Verilog simulator. o Worked on the optimization of the Verilog compiler, performance analysis and improvements of the simulator software. ### R&D engineer @ Cadence Design Systems Jan 2008 – Jan 2009 * Implemented code generator to create timed SystemC models from SysML state charts. This work was part of System level modeling and design tool. * Represented Cadence at Accellera standards organization and contributed to the standardization of Standard Co-Emulation Modeling Interface (SCE-MI 2.1). ### Graduate student researcher @ Center for Embedded Computer Systems Jan 2003 – Jan 2008 * Designed source-level code transformations for creating parallel and analyzable System-on-Chip (SoC) models * Developed compiler and design tool for a C-ish system level modeling language * Designed Source Re-Coder, an interactive GUI for re-coding SoC models, in order to create explicit parallel models from sequential C code. This interactive tool resulted in two orders of gain in design productivity compared to manual recoding work. *Developed of system level models of embedded systems for video and audio decoding applications. ### Firmware Engineer @ Broadcom Jan 2000 – Jan 2003 * Developed firmware for video and audio decoding for different set-top box projects. This work was awarded two patents. * Developed System level models of SoC architectures meant for HD video decoding in C++/SystemC ## Education ### Ph.D. in Embedded Computer Systems and Software UC Irvine ### B.E. in Electronics and Communication Engineering University of Mysore ## Contact & Social - LinkedIn: https://linkedin.com/in/pramodchandraiah - Portfolio: http://www.cecs.uci.edu/~pramodc/ --- Source: https://flows.cv/pramodchandraiah JSON Resume: https://flows.cv/pramodchandraiah/resume.json Last updated: 2026-04-11