# Prasun Raha > Rivian | Autonomy HW Systems Location: Palo Alto, California, United States Profile: https://flows.cv/prasun With over 20 years of engineering experience in system engineering & compute platforms, I am a seasoned hardware architect who leads the HW Platform Architecture team at Rivian. I have extensive expertise in hardware design, analog semiconductors, circuit design, and system validation, as well as multiple publications and patents in these fields. At Rivian, I help define the next generation platform architecture for sensors, compute, perception, and networking, enabling emissions-free electric adventure vehicles that challenge what’s possible. I am passionate about Rivian’s mission to keep the world adventurous forever and the opportunity to contribute to the transition to sustainable transportation. I thrive on collaborating with talented engineers, designers, and innovators to create cutting-edge solutions for emerging applications on the edge. ## Work Experience ### VP, Autonomy Compute and Sensing Systems @ Rivian Jan 2021 – Present | Palo Alto, CA Building autonomy compute & sensing systems to enable deployment of advanced autonomy on Rivian platforms ### Sr Director, System validation and applications @ Xilinx Jan 2020 – Jan 2021 | San Francisco Bay Area Engineering the next generation Adapatible Compute PLatforms for Machine Learning, 5G, ADAS and Industrial Automation ### Director, System Validation @ Xilinx Jan 2015 – Jan 2020 | San Jose, CA Engineering the next generation Programmable SoCs for Artifical Intelligence, Realtime compute and 5G signal processing ### Sr. Director, Systems @ Tabula Jan 2010 – Jan 2015 Built a global system engineering team from scratch to deliver state of the art platform solutions for high end networking applications like TOR switches, Search acceleration engines, High-end Packet Processing solutions targeted for a more flexible datacenter. ### Director, Analog Systems @ Tabula Jan 2007 – Jan 2010 Design management for a state of the art 22nm and 40nm SoC for Networking Applications - High speed serial interfaces : Multi-protocol serdes with integrated 10/40/100G ethernet interfaces - High performance memory interfaces : DDR3 PHY with integrated high speed memory controllers - Clocking and clock distribution includes Core PLL, DLLs and clocking architecture Lead architecture, design and bringup efforts of overall SoC and its constituent components. Program management and reporting on schedules to exective staff. ### Sr. Design Manager @ Xilinx Jan 2004 – Jan 2007 Managed high speed multi-protocol Serdes on the 65nm;Virtex-5 generation of products ranging from datarates of 1.25Gbps to 6.5Gbps. ### Design Manager @ Texas Instruments Jan 2001 – Jan 2004 Responsible for design of high speed serial IO interface for high performance microprocessor design. Responsible for development of Phase locked loops / Delay locked loops and other key analog IP enabling the 65nm generation of TI DSPs. ### Hardware Design Engineer @ Agilent Technologies Jan 1997 – Jan 2001 High Speed IO design for networking applications and Printer ASICs ## Education ### PhD in Electrical Engineering University of Illinois Urbana-Champaign ### AEA/ Stanford Executive Institute in Entrepreneurial and Small Business Operations Stanford University ### Master of Science (MS) in EE, Electrical, Electronics and Communications Engineering Old Dominion University ### B.Tech in Electrical Engineering Indian Institute of Technology, Kharagpur ## Contact & Social - LinkedIn: https://linkedin.com/in/prasunraha --- Source: https://flows.cv/prasun JSON Resume: https://flows.cv/prasun/resume.json Last updated: 2026-04-13