# Priyanka Thakore > Chief Architect | Board Member | Silicon Architect | Expertise in SoC/ASIC Design, Low-Power, NVMe, and NAND | 20+ Years in Flash Storage and Semiconductor| 15+ Patents | Leader in Cross-Functional & Global Collaboration Location: San Jose, California, United States Profile: https://flows.cv/priyankathakore As a Silicon Architect, I specialize in designing high-performance, power-efficient SoC/ASIC solutions that drive innovation in Flash storage and computing. With 18+ years of experience, I have shaped the architecture of industry-leading products, from startups to large-scale semiconductor companies. My expertise spans from defining product roadmaps to aligning cross-functional and international teams toward shared product milestones, ensuring seamless execution from concept to production. ► Led SoC/ASIC Architecture, designing four ASICs from the ground up, shipping millions of units with first-time-right silicon, and developing proprietary on-chip communication protocols alongside AMBA standards. ► Drove Performance & Power Modeling, optimizing SSD systems, including DRAM integration, to achieve efficient SoC roadmaps. Spearheaded SystemC modeling to guide architectural tradeoffs for best-in-class power-performance efficiency. ► Led Internal IP RTL Development, overseeing implementation and verification of custom silicon solutions to drive product differentiation. ► Managed NAND Flash Vendor Relations & 3rd Party IP Vendor Management, aligning with ONFI/JEDEC/Flash Vendors as well as Silicon IP vendors and fostering key partnerships to ensure scalable, high-quality silicon. ► Architected Low-Power Solutions, optimizing ASIC designs for energy efficiency while maintaining high performance, ensuring best-in-class power and thermal management. Specialties: SoC/ASIC Architecture | Low-Power Architecture | Product Roadmapping | PCIe/NVMe | Flash & 3D XPoint Memory | AMBA AXI | SystemC Performance Modeling | Power & Performance Optimization | Quality of Service (QoS) | CPU (RISC-V, ARM) | 3rd Party IP Vendor Management | Internal IP Development | Cross-Functional & International Team Leadership ## Work Experience ### Chief Architect @ TenaFe Inc Jan 2019 – Present Develop company-wide product Roadmap. Develop MRD,PRD and SoC (System-on-Chip) integration and ASIC design roadmap for next-gen storage solutions. Define low-power architecture, optimizing clock, power, and voltage domain management. Lead the product modeling platform with a focus on performance analysis and power modeling using SystemC. Oversee Network-on-Chip (NoC) implementation and integration of on-chip interface protocols (AMBA AXI, OCP, ONFI, JEDEC). Manage third-party IP engagement. Seamless cross-functional collaboration across global teams. ### Sr. Manager & Lead Architect for SSD Controllers @ Micron Technology Jan 2015 – Jan 2018 | Santa Clara, CA Led Micron's Internal SSD Controller Architecture Defined SSD controllers for Client OEM and Datacenter Cloud Segments Developed Quality of Service (QoS) strategies for enterprise and cloud workloads. Optimizing cache design and DRAM performance for high-performance storage. Set processes for successful multi-Functional teams engagement across international sites. Drove performance and power optimization, aligning firmware and hardware teams on efficiency goals. Collaborated with design teams on on-chip interface protocol implementation (AMBA AXI, ONFI, DDR, I3C). Worked on new products definition upcoming media technology like 3DX Point . Exercise tightly integrated working style across Design and Firmware Teams to enable working products with realistic schedules. ### Sr. Manager, Soc Architecture @ Tidal Systems Inc. ( Acquired by Micron Technology) Jan 2013 – Jan 2015 Tidal Systems was among the first startups to adopt the NVMe interface during its early standardization phase. The company was later acquired by Micron Semiconductor in a multimillion-dollar deal for its first SSD controller silicon, which was successfully productized under the Micron brand. Founding Member and key contributor to technology and product strategy. Led ASIC Architecture, driving innovation in SSD controller design. Spearheaded Product Modeling, identified bottlenecks and controller features to achieve Datacenter QOS Targets. Provided early product marketing and business development support, facilitating technical engagements with partners and investors. Hands-on Designer and lead to critical proprietary company IPs. ### Nand Characterization Lead @ Link A Media Devices (Acquired by SKHynix Inc.) Jan 2010 – Jan 2013  Setup Platform Hardware and Software to enable On-Site Automated Flash Characterization  Customer interface for all NAND vendors including Samsung, Micron, Toshiba and Hynix  Cycle through various conditions for Nand Devices to study Noise and Characteristic under various retention and endurance conditions.  Assist the development and implementation of various DSP algorithms cater towards MLC and TLC Nand devices. ### Product Owner and Manager, Soc Development @ Link A Media Devices (Acquired by SKHynix Inc.) Jan 2010 – Jan 2013 | Santa Clara, CA Delivered Multiple Product across - Client OEM value segments, - High-performance enterprise storage solutions. - Cost Sensitive Mobile-OEM segment, balancing affordability with reliability.  Project Owner/Manager and Architect for the eMMC LDPC Nand Flash Controller, driving SoC design and integration.  Responsible for customer engagement, technical and product definition.  Developed innovative low-power solutions by defining analog IPs addressing challening Low power targets in emmc storage controllers.  Involved in FW algorithm development including Flash layer Management, power interrupt schemes and workload dependent optimization.  Led cross-functional teams of 20+ engineers across design, verification, firmware, and ASIC P&R to deliver high-quality silicon on schedule.  Communication with Fab partner NEC and customer for pad, packaging and wafer probing strategies to enable multi Die packaging solutions. ### Technical Design Lead and Sr. Designer @ Link A Media Devices (Acquired by SKHynix Inc.) Jan 2007 – Jan 2013 Technical Engineering Lead for eMMC BCH Nand Flash Controller (Link-A-Media Devices) 2007 – Apr 2011  Work with Micron Mobile eMMC Team as Flash Backend Technical Lead  Hands on implementation of top level integration including Clock structure, ARM ,ONFI interface and eMMC Host interface Hybrid SSD Controller, Nov 2010 – May 2011  The first Generation product is in mass production and the same SOC is reused for the second generation product due to the design ability to support new customer requests & Nand Features.  Implemented BCH Decoder Design by Syndrome-BMA modules  Driven the Analog team to support multiple vendor SI simulations and defined Spec for Nand IO. Enterprise SSD controller I and II , June 2008- Mar 2009 , Mar 2009-Nov 2009  Part of 3 person team to develop the Hardware and FW architecture to support Enterprise requirement of variable sector size leading to patent to support cross page management.  Support production Qualification for both Enterprise controller. First Generation Client SSD Soc Controller , Mar 2008 – Nov 2008  Owner of multiple New Modules including company’s first SSD controller Nand Device Interface, First Channel Estimation block for soft information for LDPC decoder & Hardware Automation for Command Scheduling.  Solely responsible for Micro-architecture, Implementation, verification, Timing closure, FPGA validation and Chip Bringup for above Modules. Software Experience :  Developed Nand Flash layer Firmware functions for SSD SOC FW.  Built initial development of the Verification environment and tester in C.  Integrated the PCMCIA Card for T1/E1 Link to the Client and Server in C and ported the simulator system to linux platform ### Graduate @ University of Cincinnati Jan 2004 – Jan 2007 | Ohio, United States Masters Thesis focused on making ASIC Designs Robust against the presence of Silicon Defects. - Developed DFM (Design for Manufacturability) and DFY(Design for Yield ) Resilient standard cell suite from ground up . - Developed C Based Software Suite to parse through all the Standard Cell to Analyse Nodes and enable the STD Cell Development. - Setup Backend Tools Flow Additional Research also done on Hardware Security and Trust. ### Graduate Intern @ Motorola Jan 2005 – Jan 2005 | schaumburg., Illinois  Developed Software application to integrate New PCMCIA Card into T1/E1 Link to the Client  Developed the Server application to enable handshaking and Network Protocol with the new Card  Additionally ported the simulator system to Linux platform.  Exceeded expectations by completing the massive task within 3 months including the completely new Hardware - Software automated system. ### Senior Network Engineer @ Reliance Communications Jan 2003 – Jan 2004 In Charge of Two Wider Area LAN Networks. ### Intern @ Physical Research Laboratory, India Jan 2002 – Jan 2003 Developed Chirp Z Transform Electronic Spectrometer to be dispatched on Satellite to sample sub particle frequencies. The high-resolution spectroscopy is of great importance for studying the wind velocity, temperature, pressure, and chemical composition of the astronomical targets emitting signal in sub-millimeter (SMM) range of frequencies. The spectral information of molecular transitions of an astronomical source can be retrieved by processing the IF signal from a mixer device through a spectrometer. The instrument design consuming low power of few Watts only, essential for space payloads. The chirp transform of signal f (t) is derived from the Fourier transformation ## Education ### MSEE University of Cincinnati ### BE Nirma Institute of Technology ## Contact & Social - LinkedIn: https://linkedin.com/in/priyanka-thakore - Website: http://www.link-a-media.com --- Source: https://flows.cv/priyankathakore JSON Resume: https://flows.cv/priyankathakore/resume.json Last updated: 2026-04-05