• Designed an ultra-low power FinFET based 6T SRAM cell, operating at subthreshold region, with separate read and write paths to make the cell read Static Noise Margin free.

• Implemented single bit line scheme to improve the Write dynamic power consumption and optimized the sizing to improve write ability of the proposed cell.

• Compared the performance (in terms of Power Delay Product) of the proposed cell with the conventional 5T, 6T and 8T cells.

• Negative word line scheme is imposed over both read and write word lines to reduce the leakage power of the proposed cell considerably compared to other cells.

• The cell is operated over different temperatures and supply voltages to ensure that the cell withholds PVT variations.