Accomplished Senior Technical lead and software professional with deep experience in Linux, device driver, and Optics. Proven success in achieving deadlines and delivering quality product development to clients. Experienced in routing, switching, and wireless products.
Experience
2021 — Now
2021 — Now
San Jose, California, United States
Optical Systems Division (OSD)
2015 — 2020
San Jose
Worked with a team to architect and develop Next Generation Catalyst 9300 and 9500 Switches. Primarily worked with kernel and userspace drivers for UADP 2.0 packet processor initialization and DMA mappings. Also, participated in UADP 2.0 bring-up and data-path ping. Worked with MPLS l2VPN features VPLS and PWRoVLAN for a key airport customer. Worked on the development of Wi-Fi 6 enterprise-grade outdoor access point (Catalyst 9124AX)
2008 — 2015
San Jose
Overall Technical lead for the development of three generations of Line cards for the ASR9000 platform.
• Took the lead in Optics and PHY driver development
• Worked with HW leads in defining next generation PHY development
• Successfully added SW support for Copper (RJ45) and 100FX Optical SFPs
• WAN-PHY and OTN development
• Developed a proof of concept OTN Linecard with Acacia Coherent Optical module
• Developed 16x10G Line card
This was a time to market product. Worked with HW, EDVT, ODVT, and PHY vendor to fix several issues. Delivered a quality product to customers.
• UDFD: (Uni-directional Fault Detection):
1GE doesn’t support RFI (Remote fault indication). Worked with PI and PD EOAM teams to deliver this feature
• UDLR (uni-directional link routing):
A specific customer requested to add Uni-Directional Link Routing (UDLR) to 10GE interfaces.
I provided the architecture and implementation details
• Modular line card with pluggable Ethernet Adapter:
Lead the program from the SW side. Brought up 2-NPU, 4-NPU Line cards, and 20x1GE and 2x10GE, 4x10GE Ethernet Port (EP) Adapters. Wrote PHY, FPGA drivers to EPs. Supported Triages, dev-test, EDVT, ODVT, HALT, MFG
• PQ60 PHY driver:
Sole lead for successfully delivering a PHY driver which is used in multiple line cards and Ethernet port adapters.
• Developed 2x40GE Ethernet Port Adapter
2002 — 2007
San Jose, California, United States
• OC48/DS3 SONET SPA development
◦ Worked with the hardware team to design and develop a channelized SONET Sharable
Port Adapter (SPA)
◦ Wrote a software document and developed a framer application in QNX OS
◦ Created a software document for third-party vendor API development
◦ Developed a framer level software for APS, BERT, dual-queue and mixed-mode operation
◦ Worked with GSR/IOX platform to bring up and successfully complete QA
• OC3/OC12 SONET SPA development
◦ Developed a platform and OS independent framer driver for three SONET /SDH SPAs (1xOC12, 2xOC3, 4xOC3)
◦ Worked with c7600/SIP1, c7600/SIP2, GSR/MOD48, c7300/Starlifter, and CRS-1/Tuxedo platform groups to integrate the SPA software
◦ The SPAs passed EDVT, compliance, and manufacturing tests successfully before they were shipped to customers.
• 2xOC48 Packet over SONET/DPT line card development
◦ Worked with the hardware team to design and develop a line card for the c7600 platform
◦ Dynamic Packet Switching (DPT) used Cisco’s SRP protocol to implement SONET on a ring
◦ The single product supported two different features (2xOC48 POS or 1xOC48 DPT).
◦ Wrote framer driver and alarm handling code
◦ Also, ported SRP protocol code from 12.0S branch to 12.1 branches
◦ The line card has two Toaster Packet processors.
◦ Worked with the Packet Processor team to define the algorithm for SRP packet handling
1995 — 2001
San Jose, California, United States
1xOC48 POS line card development:
Developed Line card software and Skystone SONET Framer driver for c7600 platform. Worked with Toaster Packet processor team during the line card development. Added Framer APS, Alarm and PMON
support. After successful completion of EDVT, SONET Compliance, manufacturing, and dev-test, the product was shipped to customers.
Cat6000/c7600 Rommon development:
Implemented AMDFE Fast-Ethernet driver, Buffer Management and SCP handling code in ROM monitor for RISC CPU to download Line card image from Route-processor (RP) bundle. Also, added code to export LC crash info to RP.
C7200/NPE175/NPE225 CPU card development:
Developed ROM monitor for RISC CPU and system software for NPE-175 and NPE-225 CPU cards for c7200 router platform. Sole software developer for this project. The product was Delivered to customers after successful dev-test cycle. Also, developed software for c7202, a two slot router for c7200 family.
AS5800 platform support:
Developed remote file system (RFS) feature. The RFS interconnected C7200 Router-shelf with a Dial-shelf. Also, worked with the team to Fix many dev-test found platform software bugs.
JT2 and E1-G703 PCI Port-adapter development:
Designed and developed software for Japanese T2 (6.321 Mbps) and E1-G703 PCI port adapters. The Framer driver, alarm and signal handler are used in c7200 and c7500/VIP2 platforms.
AGS+, c7000, c7500, C7200 Platform SW development:
Fixed few AGS+ bugs during my sustaining work. Fixed many ucode bugs in FSIP (8T1/8E1) line card used in c7000 and C7500 platforms. The ucode was written in 68000 assembly language. Also, participated in the development of c7200 platform. Fixed many bugs in particle-based IOS application code.
Education
College of Engineering at Tennessee Technological University
Master of Science (MS)
College of Engineering, Guindy
Master of Engineering (MEng)
College of Engineering, Guindy